Add basic support for .cfi_personality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122566 91177308-0d34-0410-b5e6-96231b3b80d8

move isBytewiseValue out to ValueTracking.h/cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122565 91177308-0d34-0410-b5e6-96231b3b80d8

actually add the file...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122563 91177308-0d34-0410-b5e6-96231b3b80d8

Start of a pass for recognizing memset and memcpy idioms.
No functionality yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122562 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122561 91177308-0d34-0410-b5e6-96231b3b80d8

fix some sort of weird pasto

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122560 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122559 91177308-0d34-0410-b5e6-96231b3b80d8

Generalize a previous change, fixing PR8855 - an valid large immediate
rejected by the mc assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8

don't lose TD info

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122556 91177308-0d34-0410-b5e6-96231b3b80d8

switch the inliner alignment enforcement stuff to use the
getOrEnforceKnownAlignment function, which simplifies the code
and makes it stronger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122555 91177308-0d34-0410-b5e6-96231b3b80d8

Move getOrEnforceKnownAlignment out of instcombine into Transforms/Utils.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122554 91177308-0d34-0410-b5e6-96231b3b80d8

Support/PathV1: Deprecate makeAbsolute and remove Unix impl because it annoys people.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122553 91177308-0d34-0410-b5e6-96231b3b80d8

Header warning patrol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122551 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a thinko pointed out by Frits van Bommel: looking through global variables in isBytewiseValue is not safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122550 91177308-0d34-0410-b5e6-96231b3b80d8

Merge IsFixupFullyResolved and IsSymbolRefDifferenceFullyResolved. We now
have a single point where targets test if a relocation is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122549 91177308-0d34-0410-b5e6-96231b3b80d8

MemCpyOpt: Turn memcpys from a constant into a memset if possible.

This allows us to compile "int cst[] = {-1, -1, -1};" into
  movl  $-1, 16(%rsp)
  movq  $-1, 8(%rsp)
instead of
  movl  _cst+8(%rip), %eax
  movl  %eax, 16(%rsp)
  movq  _cst(%rip), %rax
  movq  %rax, 8(%rsp)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122548 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Start handling some Thumb branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122547 91177308-0d34-0410-b5e6-96231b3b80d8

Minor cleanup related to my latest scheduler changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122545 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122544 91177308-0d34-0410-b5e6-96231b3b80d8

Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122542 91177308-0d34-0410-b5e6-96231b3b80d8

Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8

whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify a check for implicit defs and remove a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122537 91177308-0d34-0410-b5e6-96231b3b80d8

In llvm-mc parse a Hash token as a full line comment.  Allows handling of
preprocessed .s files and matches darwin gas.  rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122531 91177308-0d34-0410-b5e6-96231b3b80d8

Use a StringSwitch<> instead of a manually constructed string matcher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122530 91177308-0d34-0410-b5e6-96231b3b80d8

When determining if we can fold (x >> C1) << C2, the bits that we need to verify are zero
are not the low bits of x, but the bits that WILL be the low bits after the operation completes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122529 91177308-0d34-0410-b5e6-96231b3b80d8

Code clean up. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122528 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122524 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize a few more documented register name aliases for ARM in the asm lexer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8

Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122521 91177308-0d34-0410-b5e6-96231b3b80d8

Do not re-test for the existence of pthread.h.

It was causing problems on the MinGW build. See PR8849.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122518 91177308-0d34-0410-b5e6-96231b3b80d8

XFAIL vg_leak the new test as the rest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122517 91177308-0d34-0410-b5e6-96231b3b80d8

It is possible for SimplifyCFG to cause PHI nodes to become redundant too late in the optimization
pipeline to be caught by instcombine, and it's not feasible to catch them in SimplifyCFG because the
use-lists are in an inconsistent state at the point where it could know that it need to simplify them.
Instead, have CodeGenPrepare look for trivially redundant PHIs as part of its general cleanup effort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122516 91177308-0d34-0410-b5e6-96231b3b80d8

Flag -> Glue, the ongoing saga

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8

flags -> glue for selectiondag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8

sdisel flag -> glue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122507 91177308-0d34-0410-b5e6-96231b3b80d8

continue renaming flag -> glue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122506 91177308-0d34-0410-b5e6-96231b3b80d8

Fix OCaml bindings crash, PR8847.

See http://caml.inria.fr/mantis/view.php?id=4166
If we call only external functions from a module, then its 'let _' bindings
don't get executed, which means that the exceptions don't get registered for use
in the C code.
This in turn causes llvm_raise to call raise_with_arg() with a NULL pointer and
cause a segmentation fault.

The workaround is to declare all 'external' functions as 'val' in these .mli
files.

Also added a separate testcase (the testcase must call only external functions
for the bug to occur).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122497 91177308-0d34-0410-b5e6-96231b3b80d8

Remove/fix invalid README entries. The well thought out strcpy function doesn't return a pointer to the end of the string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122496 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some obsolete README items, add a new one off the top of my head.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122495 91177308-0d34-0410-b5e6-96231b3b80d8

Reorganize ListScheduleBottomUp in preparation for modeling machine cycles and instruction issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122491 91177308-0d34-0410-b5e6-96231b3b80d8

Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows multiple nodes per cycle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122474 91177308-0d34-0410-b5e6-96231b3b80d8

In CheckForLiveRegDef use TRI->getOverlaps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122473 91177308-0d34-0410-b5e6-96231b3b80d8

Fixes PR8823: add-with-overflow-128.ll
In the bottom-up selection DAG scheduling, handle two-address
instructions that read/write unspillable registers. Treat
the entire chain of two-address nodes as a single live range.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122472 91177308-0d34-0410-b5e6-96231b3b80d8

Preserve the address space when generating bitcasts for MemTransferInst in ConvertToScalarInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122462 91177308-0d34-0410-b5e6-96231b3b80d8

Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8

Default to armv7 instead of armv6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122457 91177308-0d34-0410-b5e6-96231b3b80d8

Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122456 91177308-0d34-0410-b5e6-96231b3b80d8

DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal.  The latter usually compiles into smaller code.

example code:
unsigned foo(unsigned x, unsigned y) {
  if (x != 0) y--;
  return y;
}

before:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    sbbl  %eax, %eax              ## encoding: [0x19,0xc0]
    notl  %eax                    ## encoding: [0xf7,0xd0]
    addl  8(%esp), %eax           ## encoding: [0x03,0x44,0x24,0x08]
    ret                           ## encoding: [0xc3]

after:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    movl  8(%esp), %eax           ## encoding: [0x8b,0x44,0x24,0x08]
    adcl  $-1, %eax               ## encoding: [0x83,0xd0,0xff]
    ret                           ## encoding: [0xc3]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8

InstCombine: creating selects from -1 and 0 is fine, they combine into a sext from i1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122453 91177308-0d34-0410-b5e6-96231b3b80d8

X86: Lower a select directly to a setcc_carry if possible.

  int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122451 91177308-0d34-0410-b5e6-96231b3b80d8

Add r122359 back now that the bug in MCDwarfLineAddrFragment fragment has been
fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122448 91177308-0d34-0410-b5e6-96231b3b80d8

Constify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122447 91177308-0d34-0410-b5e6-96231b3b80d8

Assert that the AddrDelta expression is really constant and wrap it in a set
if we have a lame assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122446 91177308-0d34-0410-b5e6-96231b3b80d8

When RegAllocGreedy decides to spill the interferences of the current register,
pick the victim with the lowest total spill weight.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122445 91177308-0d34-0410-b5e6-96231b3b80d8

Include a shadow of the original CFG edges in the edge bundle graph.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122444 91177308-0d34-0410-b5e6-96231b3b80d8

Rename NeedsSetToChangeDiffSize to HasAggressiveSymbolFolding which is a much
better name and matches what is used in the MachO writer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122443 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122441 91177308-0d34-0410-b5e6-96231b3b80d8

Add reduced test from 8845.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122438 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r122359 while I debug PR8845.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122427 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another conditional expression mismatched enum type warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122419 91177308-0d34-0410-b5e6-96231b3b80d8

When determining whether the new instruction was already present in
the original instruction, half the cases were missed (making it not
wrong but suboptimal).  Also correct a typo (A <-> B) in the second
chunk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122414 91177308-0d34-0410-b5e6-96231b3b80d8

Make this test not depend on how the variable is named.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122413 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is
esp. important given that the LOCAL_SECTDIFF enumeration got redefined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122412 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Clone off an ARM version of RecordScatteredRelocation until I figure out how it is supposed to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122410 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O: Return to reporting errors if we see unexpected fixup kinds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122409 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Recognize generic _Data_N fixup kinds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122408 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Add enough relocation logic to get BR24 relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122407 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Fix thinko.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122406 91177308-0d34-0410-b5e6-96231b3b80d8

Use references and simplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122405 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify the handling of .size expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122404 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O/ARM: Stub out RecordARMRelocation, which is mostly a copy of
RecordRelocation with lots of FIXMEs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122402 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122401 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O: Split out RecordARMRelocation for now, it is weird enough it isn't
clear how to keep in the generic path (yet).
 - Will revisit when it actually works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122400 91177308-0d34-0410-b5e6-96231b3b80d8

Add a generic expansion transform: A op (B op' C) -> (A op B) op' (A op C)
if both A op B and A op C simplify.  This fires fairly often but doesn't
make that much difference.  On gcc-as-one-file it removes two "and"s and
turns one branch into a select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122399 91177308-0d34-0410-b5e6-96231b3b80d8

ptx: add ld instruction and test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122398 91177308-0d34-0410-b5e6-96231b3b80d8

Add some statistics, good for understanding how much more powerful
instcombine is compared to instsimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122397 91177308-0d34-0410-b5e6-96231b3b80d8

Fixes file extension for loadable modules on OS X.

Patch by Wesley Peck!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122395 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in ReduceLoadWidth that wasn't handling extending
loads properly.  We miscompiled the testcase into:

_test:                                  ## @test
movl $128, (%rdi)
movzbl 1(%rdi), %eax
ret

Now we get a proper:

_test:                                  ## @test
movl $128, (%rdi)
movsbl (%rdi), %eax
movzbl %ah, %eax
ret

This fixes PR8757.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122392 91177308-0d34-0410-b5e6-96231b3b80d8

more cleanups, move a check for "roundedness" earlier to reject
unhanded cases faster and simplify code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122391 91177308-0d34-0410-b5e6-96231b3b80d8

reduce indentation and improve comments, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122389 91177308-0d34-0410-b5e6-96231b3b80d8

Don't generate carry bit when loading immediate values on the Microblaze.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122385 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for some of the LLVM atomic operations to the MBlaze backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122384 91177308-0d34-0410-b5e6-96231b3b80d8

Modeling the carry bit in the MSR register of the MicroBlaze.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122381 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a regression introduced into the MBlaze delay slot filler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122379 91177308-0d34-0410-b5e6-96231b3b80d8

Give GVN back the ability to perform simple conditional propagation on conditional branch values.
I still think that LVI should be handling this, but that capability is some ways off in the future,
and this matters for some significant benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122378 91177308-0d34-0410-b5e6-96231b3b80d8

GCC objects to the two sides of a conditional expression having different enum
types, but they're just getting converted to unsigned anyway, so cast first
(and ask questions later).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122377 91177308-0d34-0410-b5e6-96231b3b80d8

Remove dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122371 91177308-0d34-0410-b5e6-96231b3b80d8

In DelayForLiveRegsBottomUp, handle instructions that read and write
the same physical register. Simplifies the fix from the previous
checkin r122211.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122370 91177308-0d34-0410-b5e6-96231b3b80d8

whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122368 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply 122353-122355 with fixes.  122354 was wrong;
the shift type was needed one place, the shift count
type another.  The transform in 123555 had the same
problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122366 91177308-0d34-0410-b5e6-96231b3b80d8

Add some x86 specific dagcombines for conditional increments.

(add Y, (sete  X, 0)) -> cmp X, 1; adc  0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete  X, 0), Y) -> cmp X, 1; sbb  0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y

for
  unsigned foo(unsigned a, unsigned b) {
    if (a == 0) b++;
    return b;
  }
we now get:
  foo:
    cmpl  $1, %edi
    movl  %esi, %eax
    adcl  $0, %eax
    ret
instead of:
  foo:
    testl %edi, %edi
    sete  %al
    movzbl  %al, %eax
    addl  %esi, %eax
    ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122364 91177308-0d34-0410-b5e6-96231b3b80d8

GVN's Expression is not POD-like (it contains a SmallVector). Simplify code while at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122362 91177308-0d34-0410-b5e6-96231b3b80d8

Revert 122353-122355 for the moment, they broke stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122360 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify EvaluateAsAbsolute now that EvaluateAsRelocatableImpl does all
the folding it can.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122359 91177308-0d34-0410-b5e6-96231b3b80d8

Don't relax org or align. They change size as the relaxation happens, but they
are not actually relaxed. For example, a section with only alignments will never
needs relaxation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122356 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new transform to DAGCombiner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122355 91177308-0d34-0410-b5e6-96231b3b80d8

Get the type of a shift from the shift, not from its shift
count operand.  These should be the same but apparently are
not always, and this is cleaner anyway.  This improves the
code in an existing test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122354 91177308-0d34-0410-b5e6-96231b3b80d8

Shift by the word size is invalid IR; don't create it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122353 91177308-0d34-0410-b5e6-96231b3b80d8

fix some typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122349 91177308-0d34-0410-b5e6-96231b3b80d8