Fix obvious typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35164 91177308-0d34-0410-b5e6-96231b3b80d8

Fix naming inconsistencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8

Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35162 91177308-0d34-0410-b5e6-96231b3b80d8

Constant generation instructions are re-materializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35161 91177308-0d34-0410-b5e6-96231b3b80d8

Added isReMaterializable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35160 91177308-0d34-0410-b5e6-96231b3b80d8

Recognize target instruction flag 'isReMaterializable'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8

Add a TargetInstrDescriptor flag to mark an instruction as "re-materializable".
It means the instruction can be easily re-materialized at any point. e.g.
constant generation, load from constantpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35158 91177308-0d34-0410-b5e6-96231b3b80d8

Add isStrictPositive() to APInt to determine if this APInt Value > 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35156 91177308-0d34-0410-b5e6-96231b3b80d8

Minor bug fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35153 91177308-0d34-0410-b5e6-96231b3b80d8

fix a warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35152 91177308-0d34-0410-b5e6-96231b3b80d8

add PR#

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35151 91177308-0d34-0410-b5e6-96231b3b80d8

implement the next chunk of SROA with memset/memcpy's of aggregates.  This
implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35150 91177308-0d34-0410-b5e6-96231b3b80d8

add pr#

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35149 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35148 91177308-0d34-0410-b5e6-96231b3b80d8

testcase for SROA with memset etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35147 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up this code and fix subtract miscompile.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35146 91177308-0d34-0410-b5e6-96231b3b80d8

Implement InstCombine/and-xor-merge.ll:test[12].
Rearrange some code to simplify it now that shifts are binops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35145 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35144 91177308-0d34-0410-b5e6-96231b3b80d8

minor updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35143 91177308-0d34-0410-b5e6-96231b3b80d8

This is implemented. We now generate:

entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35142 91177308-0d34-0410-b5e6-96231b3b80d8

- Merge UsedBlocks info after two virtual registers are coalesced.
- Use distance to closest use to determine whether to abort coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35141 91177308-0d34-0410-b5e6-96231b3b80d8

Keep UsedBlocks info accurate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35140 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35139 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate ValueRanges across equality.

Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35138 91177308-0d34-0410-b5e6-96231b3b80d8

Silence warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35137 91177308-0d34-0410-b5e6-96231b3b80d8

Track the BB's where each virtual register is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35135 91177308-0d34-0410-b5e6-96231b3b80d8

Joining a live interval of a physical register with a virtual one can turn out
to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35134 91177308-0d34-0410-b5e6-96231b3b80d8

Use SmallSet instead of std::set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35133 91177308-0d34-0410-b5e6-96231b3b80d8

If sdisel has decided to sink GEP index expression into any BB. Replace all uses
in that BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35132 91177308-0d34-0410-b5e6-96231b3b80d8

GEP index sink test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35131 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for X86 inline asm constraint 'I'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35130 91177308-0d34-0410-b5e6-96231b3b80d8

Support 'I' inline asm constraint.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35129 91177308-0d34-0410-b5e6-96231b3b80d8

Only ARMv6 has BSWAP.
Fix MultiSource/Applications/aha test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35128 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on GEP index sinking by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35127 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35126 91177308-0d34-0410-b5e6-96231b3b80d8

And now support for MMX logical operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35125 91177308-0d34-0410-b5e6-96231b3b80d8

Sink a binary expression into its use blocks if it is a loop invariant
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35123 91177308-0d34-0410-b5e6-96231b3b80d8

Added isLegalAddressExpression(). Only allows X +/- C for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35122 91177308-0d34-0410-b5e6-96231b3b80d8

Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35121 91177308-0d34-0410-b5e6-96231b3b80d8

These forward declarations are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35120 91177308-0d34-0410-b5e6-96231b3b80d8

Add more comments and update to new asm syntax.

Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35119 91177308-0d34-0410-b5e6-96231b3b80d8

Multiplication support for MMX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35118 91177308-0d34-0410-b5e6-96231b3b80d8

Debugging output stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35117 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35116 91177308-0d34-0410-b5e6-96231b3b80d8

Revert last changes as they introduced other problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35115 91177308-0d34-0410-b5e6-96231b3b80d8

ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35114 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35113 91177308-0d34-0410-b5e6-96231b3b80d8

The sign information was not propagating into the rename map so only the
last entry stored in the map could be retrieved for a given integer type.
Propagating the sign information required an invasive change to ensure that
all ValueRef (ValID) instances get the right sign information as well. Also,
put in some assertions to ensure the RenameMap always gives us out the type
that is expected.

This fixes PR1256 and
test/Assembler/2007-03-14-UgpradeLocalSignless.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35112 91177308-0d34-0410-b5e6-96231b3b80d8

For PR1256:
Carry sign with ValID and make TypeInfo sortable (useful in a map).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35111 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for PR1256.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35110 91177308-0d34-0410-b5e6-96231b3b80d8

Estimate a cost using the possible number of scratch registers required and use
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35109 91177308-0d34-0410-b5e6-96231b3b80d8

Under X86-64 large code model, do not emit 32-bit pc relative calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35108 91177308-0d34-0410-b5e6-96231b3b80d8

Notes about codegen issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35107 91177308-0d34-0410-b5e6-96231b3b80d8

Test that the size of a view converted object is determined by the target
type, not the source type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35106 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35105 91177308-0d34-0410-b5e6-96231b3b80d8

Oops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35104 91177308-0d34-0410-b5e6-96231b3b80d8

Change e-mail address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35103 91177308-0d34-0410-b5e6-96231b3b80d8

Add link to exception handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35102 91177308-0d34-0410-b5e6-96231b3b80d8

Adding credit for PPC changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35101 91177308-0d34-0410-b5e6-96231b3b80d8

First draft of exception handling doc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35100 91177308-0d34-0410-b5e6-96231b3b80d8

Make older versions of bison happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35099 91177308-0d34-0410-b5e6-96231b3b80d8

Fix for VS 2005 problem supplied by Morten Ofstad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35098 91177308-0d34-0410-b5e6-96231b3b80d8

X86-64 JIT is in large code model. Need stubs for direct calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35097 91177308-0d34-0410-b5e6-96231b3b80d8

x86-64 JIT stub codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35096 91177308-0d34-0410-b5e6-96231b3b80d8

Preliminary support for X86-64 JIT stub codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35095 91177308-0d34-0410-b5e6-96231b3b80d8

ShiftAmt might equal to zero. Handle this situation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35094 91177308-0d34-0410-b5e6-96231b3b80d8

Enable KnownZero/One.clear().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35093 91177308-0d34-0410-b5e6-96231b3b80d8

New test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35091 91177308-0d34-0410-b5e6-96231b3b80d8

This got better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35090 91177308-0d34-0410-b5e6-96231b3b80d8

Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8

AM2 can match 2^n +/- 1. e.g.  ldr r3, [r2, r2, lsl #2]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35088 91177308-0d34-0410-b5e6-96231b3b80d8

Zero is always a legal AM immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35087 91177308-0d34-0410-b5e6-96231b3b80d8

Correct type info for isLegalAddressImmediate() check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35086 91177308-0d34-0410-b5e6-96231b3b80d8

Test support for arrays with non-zero first index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35084 91177308-0d34-0410-b5e6-96231b3b80d8

Stack and register alignment of call arguments in the ELF ABI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35083 91177308-0d34-0410-b5e6-96231b3b80d8

ifdef out some dead code.

Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35082 91177308-0d34-0410-b5e6-96231b3b80d8

testcase for PR1244

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35081 91177308-0d34-0410-b5e6-96231b3b80d8

For expression like
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35080 91177308-0d34-0410-b5e6-96231b3b80d8

Add zextOrCopy() into APInt for convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35079 91177308-0d34-0410-b5e6-96231b3b80d8

In APInt version ComputeMaskedBits():
  1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35078 91177308-0d34-0410-b5e6-96231b3b80d8

Implement getTargetLowering() or else LSR won't be using ARM specific hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35077 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35076 91177308-0d34-0410-b5e6-96231b3b80d8

Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35075 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35074 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is
 a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35073 91177308-0d34-0410-b5e6-96231b3b80d8

Use new TargetLowering addressing modes hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35072 91177308-0d34-0410-b5e6-96231b3b80d8

More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35071 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid bug: SSE2 supports v2i64 add / sub.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35070 91177308-0d34-0410-b5e6-96231b3b80d8

Revert the last patch as it violates the conditions of sext/zext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35068 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak C++ build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35067 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak VC++ build.  Do not use identifiers starting with _ as they are reserved and
can collide with system defined names.  Windows defines _BB, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35066 91177308-0d34-0410-b5e6-96231b3b80d8

For APInt::z/sext(width), if width == BitWidth, just return *this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35065 91177308-0d34-0410-b5e6-96231b3b80d8

Add an APInt version of SimplifyDemandedBits.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35064 91177308-0d34-0410-b5e6-96231b3b80d8

Add an APInt version of ShrinkDemandedConstant.

Patch by Zhou Sheng.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35063 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid to assert on "(KnownZero & KnownOne) == 0".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35062 91177308-0d34-0410-b5e6-96231b3b80d8

In function ComputeMaskedBits():
  1. Replace getSignedMinValue() with getSignBit() for better code readability.
  2. Replace APIntOps::shl() with operator<<= for convenience.
  3. Make APInt construction more effective.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35060 91177308-0d34-0410-b5e6-96231b3b80d8

Add getSignBit() and operator<<= into APInt for convenience.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35059 91177308-0d34-0410-b5e6-96231b3b80d8

Add value ranges. Currently inefficient in both execution time and
optimization power.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35058 91177308-0d34-0410-b5e6-96231b3b80d8

Use range tests in LowerSwitch, where possible

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35057 91177308-0d34-0410-b5e6-96231b3b80d8

Add getter methods for the extremes of a ConstantRange.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35056 91177308-0d34-0410-b5e6-96231b3b80d8