Iliyan Malchev [Thu, 29 Jul 2010 21:02:17 +0000 (14:02 -0700)]
[ARM] tegra: header describing i2s registers
Signed-off-by: Iliyan Malchev <malchev@google.com>
Iliyan Malchev [Thu, 29 Jul 2010 20:57:45 +0000 (13:57 -0700)]
[ARM] tegra: add platform devices for i2s1 and i2s2
Signed-off-by: Iliyan Malchev <malchev@google.com>
Benoit Goby [Thu, 29 Jul 2010 03:16:43 +0000 (20:16 -0700)]
[ARM] tegra: Don't share tegra_usb1_resources
Don't share tegra_usb1_resources as both tegra-udc and ehci1 are loaded
in otg mode.
Change-Id: Id5c9a076572e18662b5d3e7835f638b1cc5a1e07
Signed-off-by: Benoit Goby <benoit@android.com>
Gary King [Wed, 28 Jul 2010 23:22:31 +0000 (16:22 -0700)]
[ARM] tegra: add EHCI and UDC controllers to devices.c
update harmony and ventana to use the common UDC definition, rather
than using the current duplicated definitions
Change-Id: I2e3aca674ab35305a0c516bd22e044382280d05e
Signed-off-by: Gary King <gking@nvidia.com>
Benoit Goby [Wed, 28 Jul 2010 07:10:13 +0000 (00:10 -0700)]
[ARM] tegra: Add USB PHY configuration
Configure board dependant phy settings from the board file.
Change-Id: I29f6ffe0b84a2a6eb55bade1379002f561d92d17
Signed-off-by: Benoit Goby <benoit@android.com>
Benoit Goby [Sat, 24 Jul 2010 00:02:26 +0000 (17:02 -0700)]
[ARM] tegra: Setup USB PHY as recommended by NVIDIA
This fixes enumeration issues with some devices
Change-Id: I6283a6fb49a9e4505ad388cacdd88ecf1bdf1b9d
Signed-off-by: Benoit Goby <benoit@android.com>
Benoit Goby [Thu, 22 Jul 2010 01:05:06 +0000 (18:05 -0700)]
usb: gadget: Fix tegra udc in OTG mode
Check the transceiver state before checking udc->stopped
Enable/disable the PHY and the clock on cable events
Change-Id: Id5a8a1b94f83da8060786f31181014dd1d546fc7
Signed-off-by: Benoit Goby <benoit@android.com>
Benoit Goby [Fri, 9 Jul 2010 00:00:48 +0000 (17:00 -0700)]
usb: host: Add EHCI driver for NVIDIA Tegra SoCs
Change-Id: I53c560f2c31e043f139b840f58786429ded6ec62
Signed-off-by: Benoit Goby <benoit@android.com>
Benoit Goby [Thu, 22 Jul 2010 00:44:44 +0000 (17:44 -0700)]
[ARM] tegra: usb_phy: Add tegra_usb_phy_power_off
Change-Id: If4d66b1a0f1810773b9dc9bcec0e252df947e609
Signed-off-by: Benoit Goby <benoit@android.com>
Gary King [Wed, 14 Jul 2010 01:30:59 +0000 (18:30 -0700)]
[ARM] tegra: harmony/ventana: register additional devices
register GART, pda_power, and OTG devices
Change-Id: I6dec5f765494cdc96f3395cf32fd962c87bf70b7
Signed-off-by: Gary King <gking@nvidia.com>
Gary King [Wed, 14 Jul 2010 00:16:23 +0000 (17:16 -0700)]
[ARM] tegra: ventana: add initial support for Ventana
Change-Id: I1993fda7628c623d53fd2c97649ec3533ad790e2
Signed-off-by: Gary King <gking@nvidia.com>
Gary King [Thu, 15 Jul 2010 17:06:40 +0000 (10:06 -0700)]
[ARM] tegra: harmony: add sdhci0 controller (wlan)
Change-Id: I6000b1d34e35d9291cae80e4508518d0059397f8
Signed-off-by: Gary King <gking@nvidia.com>
Colin Cross [Mon, 4 Oct 2010 06:37:45 +0000 (23:37 -0700)]
[ARM] tegra: suspend: Add iovmm suspend
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Sat, 26 Jun 2010 01:39:58 +0000 (18:39 -0700)]
[ARM] tegra: add I/O virtual memory manager interface (iovmm)
The Tegra IOVMM is an interface to allow device drivers and subsystems in
the kernel to manage the virtual memory spaces visible to I/O devices.
The interface has been designed to be scalable to allow for I/O virtual
memory hardware which exists in one or more limited apertures of the address
space (e.g., a small aperture in physical address space which can perform
MMU-like remapping) up to complete virtual addressing with multiple
address spaces and memory protection.
The interface has been designed to be similar to the Linux virtual memory
system; however, operations which would be difficult to implement or
nonsensical for DMA devices (e.g., copy-on-write) are not present, and
APIs have been added to allow for management of multiple simultaneous
active address spaces.
The API is broken into four principal objects: areas, clients, domains and
devices.
Areas
=====
An area is a contiguous region of the virtual address space which can be
filled with virtual-to-physical translations (and, optionally, protection
attributes). The virtual address of the area can be queried and used for
DMA operations by the client which created it.
As with the Linux vm_area structures, it is the responsibility of whichever
code creates an area to ensure that it is populated with appropriate
translations.
Domains
=======
A domain in the IOVMM system is similar to a process in a standard CPU
virtual memory system; it represents the entire range of virtual addresses
which may be allocated and used for translation. Depending on hardware
capabilities, one or more domains may be resident and available for
translation. IOVMM areas are allocated from IOVMM domains.
Whenever a DMA operation is performed to or from an IOVMM area, its parent
domain must be made resident prior to commencing the operation.
Clients
=======
I/O VMM clients represent any entity which needs to be able to allocate
and map system memory into I/O virtual space. Clients are created by name
and may be created as part of a "share group," where all clients created
in the same share group will observe the same I/O virtual space (i.e., all
will use the same IOVMM domain). This is similar to threads inside a process
in the CPU virtual memory manager.
The callers of the I/O VMM system are responsible for deciding on the
granularity of client creation and share group definition; depending on the
specific usage model expected by the caller, it may be appropriate to create
an IOVMM client per task (if the caller represents an ioctl'able interface
to user land), an IOVMM client per driver instance, a common IOVMM client
for an entire bus, or a global IOVMM client for an OS subsystem (e.g., the DMA
mapping interface).
Each client is responsible for ensuring that its IOVMM client's translation is
resident on the system prior to performing DMA operations using the IOVMM
addresses. This is accomplished by preceding all DMA operations for the client
with a call to tegra_iovmm_client_lock (or tegra_iovmm_client_trylock),
and following all operations (once complete) with a call to
tegra_iovmm_client_unlock. In this regard, clients are cooperatively context-
switched, and are expected to behave appropriately.
Devices
=======
I/O VMM devices are the physical hardware which is responsible for performing
the I/O virtual-to-physical translation.
Devices are responsible for domain management: the mapping and unmapping
operations needed to make translations resident in the domain (including
any TLB shootdown or cache invalidation needed to ensure coherency), locking
and unlocking domains as they are made resident by clients into the devices'
address space(s), and allocating and deallocating the domain objects.
Devices are responsible for the allocation and deallocation of domains to
allow coalescing of multiple client share groups into a single domain. For
example, if the device's hardware only allows a single address space to
be translated system-wide, performing full flushes and invalidates of the
translation at every client switch may be prohibitively expensive. In these
circumstances, a legal implementation of the IOVMM interface includes
returning the same domain for all clients on the system (regardless of
the originally-specified share group).
In this respect, a client can be assured that it will share an address space
with all of the other clients in its share group; however, it may also share
this address space with other clients, too.
Multiple devices may be present in a system; a device should return a NULL
domain if it is incapable of servicing the client when it is asked to
allocate a domain.
----------------------------------------------------------------------------
IOVMM Client API
================
tegra_iovmm_alloc_client - Called to create a new IOVMM client object; the
implementation may create a new domain or return an existing one depending on
both the device and the share group.
tegra_iovmm_free_client - Frees a client.
tegra_iovmm_client_lock - Makes a client's translations resident in the IOVMM
device for subsequent DMA operations. May block if the device is incapable
of context-switching the client when it is called. Returns -EINTR if the
waiting thread is interrupted before the client is locked.
tegra_iovmm_client_trylock - Non-blocking version of tegra_iovmm_client_lock
tegra_iovmm_client_unlock - Called by clients after DMA operations on IOVMM-
translated addresses is complete; allows IOVMM system to context-switch the
current client out of the device if needed.
tegra_iovmm_create_vm - Called to allocate an IOVMM area. If
lazy / demand-loading of pages is desired, clients should supply a pointer
to a tegra_iovmm_area_ops structure providing callback functions to load, pin
and unpin the physical pages which will be mapped into this IOVMM region.
tegra_iovmm_get_vm_size - Called to query the total size of an IOVMM client
tegra_iovmm_free_vm - Called to free a IOVMM area, releasing any pinned
physical pages mapped by it and to decommit any resources (memory for
PTEs / PDEs) required by the VM area.
tegra_iovmm_vm_insert_pfn - Called to insert an exact pfn (system memory
physical page) into the area at a specific virtual address. Illegal to call
if the IOVMM area was originally created with lazy / demand-loading.
tegra_iovmm_zap_vm - Called to mark all mappings in the IOVMM area as
invalid / no-access, but continues to consume the I/O virtual address space.
For lazy / demand-loaded IOVMM areas, a zapped region will not be reloaded
until it has been unzapped; DMA operations using the affected translations
may fault (if supported by the device).
tegra_iovmm_unzap_vm - Called to re-enable lazy / demand-loading of pages
for a previously-zapped IOVMM area.
tegra_iovmm_find_area_get - Called to find the IOVMM area object
corresponding to the specified I/O virtual address, or NULL if the address
is not allocated in the client's address space. Increases the reference count
on the IOVMM area object
tegra_iovmm_area_get - Called to increase the reference count on the IOVMM
area object
tegra_iovmm_area_put - Called to decrease the reference count on the IOVMM
area object
IOVMM Device API
================
tegra_iovmm_register - Called to register a new IOVMM device with the IOVMM
manager
tegra_iovmm_unregister - Called to remove an IOVMM device from the IOVMM
manager (unspecified behavior if called while a translation is active and / or
in-use)
tegra_iovmm_domain_init - Called to initialize all of the IOVMM manager's
data structures (block trees, etc.) after allocating a new domain
IOVMM Device HAL
================
map - Called to inform the device about a new lazy-mapped IOVMM area. Devices
may load the entire VM area when this is called, or at any time prior to
the completion of the first read or write operation using the translation.
unmap - Called to zap or to decommit translations
map_pfn - Called to insert a specific virtual-to-physical translation in the
IOVMM area
lock_domain - Called to make a domain resident; should return 0 if the
domain was successfully context-switched, non-zero if the operation can
not be completed (e.g., all available simultaneous hardware translations are
locked). If the device can guarantee that every domain it allocates is
always usable, this function may be NULL.
unlock_domain - Releases a domain from residency, allows the hardware
translation to be used by other domains.
alloc_domain - Called to allocate a new domain; allowed to return an
existing domain
free_domain - Called to free a domain.
Change-Id: Ic65788777b7aba50ee323fe16fd553ce66c4b87c
Signed-off-by: Gary King <gking@nvidia.com>
Benoit Goby [Wed, 30 Jun 2010 01:24:09 +0000 (18:24 -0700)]
usb: gadget: Use USB PHY api
Signed-off-by: Benoit Goby <benoit@android.com>
Benoit Goby [Wed, 30 Jun 2010 01:09:26 +0000 (18:09 -0700)]
[ARM] tegra: add API for enabling the USB PHYs
Moved usb phy initialization code
Added support for usb3 utmi phy
Updated the registers as recommended by Nvidia to be MUCH closer to passing the integrity tests
TODO: Add support for usb2 ulpi phy
Signed-off-by: Benoit Goby <benoit@android.com>
Gary King [Mon, 28 Jun 2010 22:01:43 +0000 (15:01 -0700)]
[ARM] tegra: harmony: remove hard-coded partition table
use the partition information provided on the kernel command line rather
than a fixed table that is subject to change.
Change-Id: I650f634bf49b8658debb75535e94f2a497ef3432
Signed-off-by: Gary King <gking@nvidia.com>
Gary King [Mon, 28 Jun 2010 22:00:10 +0000 (15:00 -0700)]
mtd/tegra_nand: don't ignore return value for add_mtd_partitions
when the mtd partition command line format is used, ignoring the
return value left err set to the number of partitions, which was
later interpreted as an error return code for tegra_nand_probe,
which caused the MTD master to be unregistered (ultimately causing
NULL pointer derefs when mounting the root partition).
Change-Id: Icebfb295810554617c56deeafc91bc22cc43bb35
Signed-off-by: Gary King <gking@nvidia.com>
Colin Cross [Sat, 15 May 2010 02:30:34 +0000 (19:30 -0700)]
[ARM] tegra: harmony: Make board init calls explicit
Signed-off-by: Colin Cross <ccross@android.com>
Change-Id: Ic14e8db00f2272de2f4ee4013bb3ab5c1951e7fe
Colin Cross [Sun, 27 Jun 2010 05:37:57 +0000 (22:37 -0700)]
[ARM] tegra: harmony: Add framebuffer platform device
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Sun, 27 Jun 2010 05:36:41 +0000 (22:36 -0700)]
[ARM] tegra: harmony: Remove android platform devices
Signed-off-by: Colin Cross <ccross@android.com>
Benoit Goby [Sat, 5 Jun 2010 02:36:06 +0000 (19:36 -0700)]
usb: gadget: Add support for OTG
Based on work by Nvidia
Signed-off-by: Benoit Goby <benoit@android.com>
Andrei Warkentin [Mon, 28 Jun 2010 22:59:01 +0000 (17:59 -0500)]
w1: master: tegra_w1: Adds generic mach-tegra w1 support.
This adds w1 as a device for mach-tegra boards, fixes wrong
OWR I/O base, and changes OWR clock name.
Change-Id: Idffbdbd05f383ce8e423ee301e197e230db4f2f9
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
Andrei Warkentin [Mon, 28 Jun 2010 22:56:06 +0000 (17:56 -0500)]
w1: master: tegra_w1: Add initial Tegra W1 master driver
Initial implementation of W1 master driver for Tegra SoCs.
Tested with DS2781 slave driver.
Change-Id: I6cda1ea152d25a789ae6cdca96b710da72884033
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
Gary King [Wed, 4 Aug 2010 00:46:59 +0000 (17:46 -0700)]
[ARM] tegra: add a header defining tegra 2 wake pads
wakeup from LP0 is latched at the pads rather than in the interrupt
controller; since the pad numbers don't correspond to any other
sane numbering or naming system, provide a new list of defines
to make board code easier to read and maintain
Change-Id: Icf85a5826acc567452c0a2475c5a06ed042f66b3
Signed-off-by: Gary King <gking@nvidia.com>
Colin Cross [Mon, 4 Oct 2010 03:20:10 +0000 (20:20 -0700)]
[ARM] tegra: enable ARM errata 742230
Change-Id: I25b9e7c266147163ca1dcf7619db0580ff9888d8
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Tue, 8 Jun 2010 03:50:12 +0000 (20:50 -0700)]
video: tegrafb: Enable host1x clock
Change-Id: If1e50ed661493cb06de5e5bbc5ee2b0966297b4f
Signed-off-by: Colin Cross <ccross@android.com>
Iliyan Malchev [Wed, 26 May 2010 21:21:21 +0000 (14:21 -0700)]
[ARM] tegra: add FIQ support
Signed-off-by: Iliyan Malchev <malchev@google.com>
Colin Cross [Sat, 15 May 2010 02:29:18 +0000 (19:29 -0700)]
[ARM] tegra: Move common platform_device_register into boards
Signed-off-by: Colin Cross <ccross@android.com>
Erik Gilling [Thu, 22 Apr 2010 22:59:50 +0000 (15:59 -0700)]
[ARM] tegra: add spi platform devices
Signed-off-by: Erik Gilling <konkers@android.com>
Colin Cross [Mon, 4 Oct 2010 05:06:14 +0000 (22:06 -0700)]
[ARM] tegra: delay: Use immediates instead of literals
Change-Id: I4629398863062e3f80303c84d0fd3b7a4ed6e708
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Sun, 25 Apr 2010 07:29:45 +0000 (00:29 -0700)]
[ARM] tegra: Add arch-specific udelay using TMRUS
Change-Id: If075117642a725ee2ee24a622068274e588a5bc1
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Sun, 25 Apr 2010 07:29:07 +0000 (00:29 -0700)]
[ARM] Add ARCH_PROVIDES_UDELAY config option
Change-Id: Ife690c9d055fc0f17a52d2b29048af5062a664a6
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Thu, 15 Apr 2010 21:06:44 +0000 (14:06 -0700)]
[ARM] tegra: tegrafb: Free irq in probe error case and remove function
v3: Fixes from review by Jaya Kumar
- Free irq in probe error case and remove function
Change-Id: Id6ebb8b79a738d0e3a9ac63fddd785f5652982f7
CC: Jaya Kumar <jayakumar.lkml@gmail.com>
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 22 Feb 2010 03:39:55 +0000 (19:39 -0800)]
[ARM] tegra: Add framebuffer driver
v2: Fixes from review by Russell King
- Use proper return values
v2: Fixes from review by Jaya Kumar
- Comments on lcd resolution
- Remove stub functions
- Change DUMP_REG to pr_debug
- Add unregister_framebuffer to tegra_plat_remove
v2: from Colin Cross
- adjust debugging
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Erik Gilling <konkers@android.com>
Erik Gilling [Wed, 31 Mar 2010 20:49:16 +0000 (13:49 -0700)]
[ARM] tegra: move sdhci and i2c to generic devices.c
Change-Id: Ib8d500cb868663d851af5e849815bc2a1312f659
Signed-off-by: Erik Gilling <konkers@android.com>
Todd Poynor [Thu, 16 Sep 2010 22:26:37 +0000 (15:26 -0700)]
tegra: i2c: recover from spurious interrupt storm
Re-init the I2C controller when an IRQ arrives with no
I2C_INT_STATUS bits set to indicate why the interrupt was sent.
Storms of such mystery interrupts are infrequently seen.
Dump some more status when these interrupts arrive. Set an error
for the current request and wake up the requester (rather than
timing out the request or possibly silently ignoring the interrupts).
If the I2C block is inside the DVC, also ACK the DVC I2C transfer
done interrupt in the ISR error return path, as is done for the
normal return path.
Change-Id: I625b5c245aa8d83dbd7ff076b0fb5cc5682fffa1
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Colin Cross [Sat, 7 Aug 2010 02:37:07 +0000 (19:37 -0700)]
i2c: tegra: Add reset in init back
The tegra i2c controller requires a reset after an error. Put the
reset back in the init function.
Signed-off-by: Colin Cross <ccross@google.com>
Colin Cross [Fri, 6 Aug 2010 21:35:00 +0000 (14:35 -0700)]
i2c: tegra: Remove reset during init
Colin Cross [Thu, 29 Jul 2010 23:32:57 +0000 (16:32 -0700)]
i2c: i2c-tegra: Fix warning
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 28 Jul 2010 22:17:50 +0000 (15:17 -0700)]
i2c: i2c-tegra: Fix checkpatch issues, remove debugging
Change-Id: Icba24ebb1753619fcb039cbcf98487627f274744
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Wed, 14 Jul 2010 01:56:40 +0000 (18:56 -0700)]
i2c-tegra: add support for virtual busses with dynamic pinmuxing
this adds support for dynamically reprogramming the I2C controller's
pin mux on transaction boundaries to enable one controller to be
registered as multiple I2C bus adapters with the kernel. this allows
platform designers an additional tool to resolve clock rate, I/O
voltage and electrical loading restrictions between the platform's
peripherals.
the i2c-tegra platform data is extended to support this; platforms
which use this feature should pass in the number of busses which
should be created for each controller, the starting adapter number
to use and the clock rate and pin mux for each virtual bus.
Change-Id: I57a96deb7b7b793222ec3f8cc3a941917a023609
Signed-off-by: Gary King <gking@nvidia.com>
Colin Cross [Fri, 23 Jul 2010 19:55:12 +0000 (12:55 -0700)]
i2c: tegra: Prevent i2c transactions after suspend
The cpufreq driver suspends very late, and may cause an i2c
transaction when the clk api calls the dvfs api, which calls
the regulator api, which calls i2c. Return an error if an
i2c transaction is requested after suspend has been called.
Change-Id: I4d92eb9c1f558758097e2dafda6fc02addf4e185
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 14 Jun 2010 23:09:46 +0000 (16:09 -0700)]
i2c: busses: i2c-tegra: Set bus speed in platform data
Change-Id: Iebc1ad5cc56d09f1df99d09dd6456c24c93cdb0b
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 14 Jun 2010 22:06:18 +0000 (15:06 -0700)]
i2c: busses: i2c-tegra: Fix bus clock rate
Change-Id: I186a7b7474c3d2504e2a4d7c1308706bb1b53004
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 14 May 2010 02:08:32 +0000 (19:08 -0700)]
[ARM] tegra: i2c: Fix i2c driver behavior on timeout/nack
Change-Id: Ia0968df649fa56d93cf3522d983fde16413e854d
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Thu, 22 Apr 2010 07:03:06 +0000 (00:03 -0700)]
[ARM] tegra: i2c: Disable clock when idle, fix dvc
Change-Id: Idca4c392134640f611ccf10edfd28fea102742fb
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 19 Mar 2010 01:01:37 +0000 (18:01 -0700)]
[ARM] tegra: Add i2c support
Signed-off-by: Colin Cross <ccross@android.com>
Erik Gilling [Fri, 26 Mar 2010 20:31:27 +0000 (13:31 -0700)]
usb: gadget: add utmip phy into to fsl_tegra_udc
Signed-off-by: Erik Gilling <konkers@android.com>
Colin Cross [Mon, 15 Mar 2010 22:06:29 +0000 (15:06 -0700)]
[ARM] tegra: HACK Enable uart and clocks in uncompress.h
Signed-off-by: Colin Cross <ccross@android.com>
Erik Gilling [Tue, 16 Mar 2010 03:40:51 +0000 (20:40 -0700)]
[ARM] tegra: add platform devices to harmony board file
Signed-off-by: Erik Gilling <konkers@android.com>
Colin Cross [Thu, 11 Mar 2010 04:43:14 +0000 (20:43 -0800)]
[ARM] tegra: harmony: Add sdhci devices
Change-Id: I29eab117c3fb237d5178d9fcf065563e656d46f2
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 3 Mar 2010 01:25:41 +0000 (17:25 -0800)]
usb: gadget: fsl_udc: wmb ep_td struct when submitting to controller
Since these get allocated dmacoherent instead of noncacheable in armv7, we need
to do wmb before handing them to hardware.
Change-Id: I413eeb6da3bfeb754c4b475b19fe5823d83d3d04
Signed-off-by: Colin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Erik Gilling [Tue, 9 Feb 2010 23:41:00 +0000 (15:41 -0800)]
usb: gadget: add preliminary Tegra support to fsl driver
Based on work by Gary King.
Further abstraction of the chipidea core support needs to be done.
Signed-off-by: Colin Cross <ccross@android.com>
Cc: Erik Gilling <konkers@android.com>
Cc: Gary King <GKing@nvidia.com>
Colin Cross [Thu, 18 Dec 2008 20:05:28 +0000 (12:05 -0800)]
[ARM] mtd: NVIDIA Tegra NAND controller driver.
Change-Id: I6f0b18c5621bcf8fb6cde8e7b05828075db72594
CC: Dima Zavin <dima@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Thu, 19 Aug 2010 21:08:38 +0000 (14:08 -0700)]
[ARM] tegra: smp: add barrier before raising GIC IPI IRQ
since the GIC registers are device memory and the IPI data is
stored in normal memory, a simple dmb is insufficient to ensure
that the data will be visible to the IPI-receiving processor
prior to the IPI handler running
Change-Id: Idaddd9f225d00ebd3a8d656fa75c401323b80138
Signed-off-by: Gary King <gking@nvidia.com>
Catalin Marinas [Tue, 9 Mar 2010 09:55:10 +0000 (09:55 +0000)]
Add "nol2x0" early param to avoid initialisation of the L2 controller
Some development platforms may have issues with this controller, so
allow easy disabling from the kernel command line. The patch also adds
a check for l2x0_disabled in the realview_pbx.c code to avoid setting
additional L2x0 registers.
Change-Id: Icbbd3e054688811200a4c96bf7e0a81c9c0ab790
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Colin Cross [Wed, 18 Aug 2010 07:19:12 +0000 (00:19 -0700)]
[ARM] tegra: dma: Fix critical data corruption bugs
Sometimes, due to high interrupt latency in the continuous mode
of DMA transfer, the half buffer complete interrupt is handled
after DMA has transferred the full buffer. When this is detected,
stop DMA immediately and restart with the next buffer if the next
buffer is ready.
originally fixed by Victor(Weiguo) Pan <wpan@nvidia.com>
In place of using the simple spin_lock()/spi_unlock() in the
interrupt thread, using the spin_lock_irqsave() and
spin_unlock_irqrestore(). The lock is shared between the normal
process context and interrupt context.
originally fixed by Laxman Dewangan (ldewangan@nvidia.com)
The use of shadow registers caused memory corruption at physical
address 0 because the enable bit was not shadowed, and assuming it
needed to be set would enable an unconfigured dma block. Most of the
register accesses don't need to know the previous state of the
registers, and the few places that do need to modify only a few bits
in the registers are the same ones that were sometimes incorrectly
setting the enable bit. This patch convert tegra_dma_update_hardware
to set the entire register, and the other users to read-modify-write,
and drops the shadow registers completely.
Also fixes missing locking in tegra_dma_allocate_channel
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Tue, 24 Aug 2010 01:37:25 +0000 (18:37 -0700)]
[ARM] tegra: Allow overriding arch_reset
Change-Id: Iba7ab5af149724dae8caab76f044e5b12d6b0436
Signed-off-by: Colin Cross <ccross@google.com>
Colin Cross [Fri, 6 Aug 2010 00:40:39 +0000 (17:40 -0700)]
[ARM] tegra: cpufreq: Disable cpufreq during suspend
Adds a SUSPEND_PREPARE notification hook to drop the frequency to
the lowest possible during suspend. This prevents the cpufreq driver
from attempting regulator calls after suspend has started - the
regulator api can call into drivers that have already been suspended.
Also adds 216MHz (off of PLLP) as the lowest CPU frequency, which
allows PLLX to be turned off.
Change-Id: I46a7f88610ce35b6f761a557905861f79bc4df0b
Signed-off-by: Colin Cross <ccross@google.com>
Gary King [Tue, 3 Aug 2010 21:53:05 +0000 (14:53 -0700)]
[ARM] tegra: iomap: Add missing devices, fix use of SZ_8
Adds gart, hdmi, and pwm controllers to mach/iomap.h
SZ_* stops at SZ_16; just use a constant value of 8 for the timer
aperture sizes.
Change-Id: I4bbf1ca37b65698f707a277575054610ee6ca445
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Fri, 16 Apr 2010 21:58:24 +0000 (14:58 -0700)]
[ARM] tegra: add CPU_IDLE driver
supports clock-gated (LP3) SMP idle mode, and power-gated (LP2) idle
mode when all slave processors are off-line
latency for LP2 idle state is calculated as a 2-sample weighted moving
average, to allow for future variations due to (e.g.) CPU frequency
scaling.
when LP2 is an allowed state (i.e., slave CPUs have been taken off-line),
LP3 will perform an hrtimer peek-ahead; this avoids waiting for the
first processor tick following an LP2 in order to run expired hrtimers
(which was causing a 1 tick delay for most user-space sleeps)
LP2 wakeup time and latency uses a 2ms hard-coded offset to account for
the CPU powergood timeout; this is reasonable for Harmony but should be
un-hardcoded for other platforms.
Change-Id: I75e36dc14341200ba85da7ef2db8a59cc487ecec
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 18 Aug 2010 07:19:27 +0000 (00:19 -0700)]
[ARM] tegra: gpio: Add support for waking from suspend
Change-Id: If692ff0e7de3d3d5a825a8b1e7989650ef9fb238
Signed-off-by: Colin Cross <ccross@google.com>
Colin Cross [Mon, 4 Oct 2010 07:25:16 +0000 (00:25 -0700)]
[ARM] tegra: irq: Add set_wake and set_type support for suspend
Change-Id: Ic18e0c92462a590b759752662bd7d67aaf8a371a
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Fri, 16 Apr 2010 21:36:45 +0000 (14:36 -0700)]
[ARM] tegra: Add suspend and hotplug support
LP2 idle mode power-gates the main CPU complex, requiring a
full processor state save and restore from a reset vector
processor context area is allocated during platform initialization
from the kernel, and mapped into the hotplug page tables (which also
serve as the initial page tables for the LP2 main processor reset)
restoring the processor from LP2 requires calculation of a system-
and APB-clock-dependent CPU power good timer value. on Harmony,
2ms is a good baseline value for this, and the APB clock is running at
13.5MHz. these values need to be un-hardcoded for other platforms.
platform-specific data (power good times, PMU capabilities, etc.) must be
specified when registering the suspend operations to ensure that platform
power sequencing restrictions are maintained
since all device interrupts (except timers) are disabled in the suspend
path, the wakeup interrupts need to be manually unmasked before entering
into a suspend state or the processor will never wake up; these forced-unmask
interrupts are re-masked immediately in the resume path to prevent the
kernel from live-locking prior to driver resume.
in both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely
perform this transition, the final shutdown procedure responsible for
* turning off the MMU and L1 data cache
* putting memory into self-refresh
* setting the DDR pads to the lowest power state
* and turning off PLLs
is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the
start of the suspend process.
in LP1 mode (like LP2), the CPU is reset and executes the code specified
at the EVP reset vector. since SDRAM is in self-refresh, this code must
also be located in IRAM, and it must re-enable DRAM before restoring the
full context. in this implementation, it enables the CPU on PLLP, enables
PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset
vector to restore the rest of the system (MMU, PLLX, coresite, etc.). the
LP2 reset vector is expected to be found in PMC_SCRATCH1, and is
initialized during system-bootup
in LP0 mode, the core voltage domain is also shutoff. as a result, all
of the volatile state in the core voltage domain (e.g., pinmux registers,
clock registers, etc.) must be saved to memory so that it can be restored
after the system resumes. a limited set of wakeups are available from LP0,
and the correct levels for the wakeups must be programmed into the PMC
wakepad configuration register prior to system shutdown. on resume, the
system resets into the boot ROM, and the boot ROM restores SDRAM and other
system state using values saved during kernel initialization in the PMC
scratch registers.
resuming from LP0 requires the boot ROM to supply a signed recovery codeblob
to the kernel; the kernel expects that the length and address of this blob
is supplied with the lp0_vec= command line argument; if not present, suspend-
to-LP0 will be disabled
for simplicity, the outer cache is shutdown for both LP0 and LP1; it
is possible to optimize the LP1 routine to bypass outer cache shutdown
and restart
to save power, SMP tegra SoCs place non-boot CPUs in reset when they
are removed from the scheduling cluster using CPU hotplug.
slave CPUs save their contexts (incl. CP15 and VFP state) out to a
reserved memory region, cancel SMP operation, and write to the SoC
reset controller to disable themselves. this is done with caches and
MMU enabled, so care is taken to ensure that all the dirty context cache
lines are cleaned out to the PoC before shutting down.
when re-enabled, slave CPUs execute a hotplug boot routine which mirrors
the initial configuration performed by secondary_startup, but after
enabling the MMU "return" to __cortex_a9_restore which restores the
saved state from the context area, and returns to platform_cpu_die.
a local page directory is maintained (initially a copy of init_mm) by
the tegra hotplug code, to ensure that all necessary context data and
text is properly mapped (including 1:1 virtual->physical mappings for
the code which re-enables the MMU); this page table will also be used
for the idle and suspend save and resume routines for the master CPU.
in pseudo-code, the hotplug startup routine is basically:
* invalidate i-cache, BTAC, TLB, exclusive monitor
* enable i-cache, branch prediction
* invalidate d-cache
* invalidate SCU tags
* enable SMP
* setup page tables to tegra_pgd
* enable MMU & d-cache
* restore CP15 from context area
* change page table pointer to context from shutdown
* restore stack registers
* return to platform_cpu_die
Includes fixes from:
Scott Williams <scwilliams@nvidia.com>
Aleksandr Frid <afrid@nvidia.com>
Vik Kasivajhula <tkasivajhula@nvidia.com>
Bharat Nihalani (bnihalani@nvidia.com)
Change-Id: I50e6a524696342f946b6117a2d7f019f401c3bbd
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Fri, 16 Apr 2010 21:49:19 +0000 (14:49 -0700)]
[ARM] tegra: timer: Add suspend wakeup and 32khz timers
the LP2 idle state can not be woken by the internal ARM timers,
so reserve the last APB system timer for use as an LP2 wakeup
trigger
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Tue, 6 Apr 2010 03:30:59 +0000 (20:30 -0700)]
[ARM] tegra: irq: Add support for suspend wake sources
Change-Id: I863c6db6deedd6fce52dc1b912cfdbc8d16f8c55
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 18 Aug 2010 07:19:58 +0000 (00:19 -0700)]
[ARM] tegra: pinmux: Add missing drive pingroups and fix suspend
Adds missing drive pingroups, saves all drive pingroups in
suspend, and restores the pinmux registers in the proper order.
Change-Id: I17155d86de946f162aa35d369e265504b177624b
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 4 Oct 2010 18:49:26 +0000 (11:49 -0700)]
[ARM] tegra: clock: Suspend fixes, and add new clocks
Save and restore pll and osc state during suspend
Add digital audio clocks
Update clk dev associations
Correct max clock frequencies
Add pll_p as additional cpu clock state
Add values to plld table
Fix register offset for sdmmc4 clock
Add blink timer to tegra2_clocks
Change-Id: I7fa71452c4a6683b586abb0a3906e39e6549d1bc
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 4 Oct 2010 15:49:49 +0000 (08:49 -0700)]
[ARM] tegra: Add prototypes for subsystem suspend functions
Change-Id: If14c826e8919f5de11331a5c45994fe7e451330a
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Mon, 4 Oct 2010 04:24:28 +0000 (21:24 -0700)]
[ARM] tegra: irqs: Update irq list
Fixes typo in INT_CPU1_PMU_INTR (original fix from Will Deacon)
Adds board irqs
Change-Id: I46c49ee4f6b8215242314622b59c9621321282f2
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Tue, 25 May 2010 00:07:46 +0000 (17:07 -0700)]
[ARM] tegra: Add api to control internal powergating
Change-Id: Ibb233ed06ad7f045504822a1ffd57852e50216ee
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 6 Aug 2010 21:29:14 +0000 (14:29 -0700)]
[ARM] tegra: Centralize macros to define debug uart base
Signed-off-by: Colin Cross <ccross@google.com>
Colin Cross [Fri, 1 Oct 2010 01:01:18 +0000 (18:01 -0700)]
[ARM] gic: Export irq chip functions
Some systems combine the GIC with an external interrupt controller.
On these systems it may be necessary to update both the GIC registers
and the external controller's registers to control IRQ behavior.
Export the irq chip functions so that these systems can define a
custom irq chip that calls into the GIC handlers.
Change-Id: I17fc4440fa2c91cc63004abf69c8e872b55c83c6
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 1 Oct 2010 00:52:45 +0000 (17:52 -0700)]
[ARM] gic: Add functions to save and restore gic state
on systems with idle states which power-gate the logic including
the gic, such as tegra, the gic distributor needs to be shut down
and restored on entry and exit from the architecture idle code
Change-Id: I17603f5ac70d65c05587d0647cce3ba87675e117
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Mon, 28 Jun 2010 23:23:01 +0000 (16:23 -0700)]
[ARM] cache_l2x0: add shutdown and restart functions
Add shutdown and restart functions to the L2X0 outer cache controller,
so that machines which need to flush and disable the outer cache
controller prior to executing the architecture reset or platform
suspend code can do so.
Change-Id: I042aae121e7ba75223ed502afb4d118b0441597e
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Gary King [Tue, 20 Apr 2010 22:20:03 +0000 (15:20 -0700)]
[ARM] l2x0: add declaration for PREFETCH_OFFSET register
Change-Id: I0fc2aba8b332697533e1396aab2e613bc7179c33
Signed-off-by: Gary King <gking@nvidia.com>
Catalin Marinas [Mon, 29 Mar 2010 12:58:11 +0000 (13:58 +0100)]
ARM: Improve the L2 cache performance when PL310 is used
With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop or spinlocks.
This patch conditionally defines the cache_wait() function and locking
primitives (rather than duplicating the functions or file).
Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when CPU_V7 is defined.
Change-Id: I23e8fc326e6c42e7b36c7b67393fa91576692b48
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Gary King [Wed, 24 Mar 2010 21:46:53 +0000 (14:46 -0700)]
ARM: enable CONFIG_CPU_IDLE support
add ARCH_HAS_CPU_IDLE_WAIT and ARCH_HAS_DEFAULT_IDLE configuration,
and expose default_idle and cpu_idle_wait
cpu_idle_wait implementation based on the implementation in the x86 tree
Signed-off-by: Gary King <gking@nvidia.com>
Erik Gilling [Thu, 22 Apr 2010 22:58:25 +0000 (15:58 -0700)]
spi: add spi_tegra driver
v2 changes:
from Thierry Reding:
* add "select TEGRA_SYSTEM_DMA" to Kconfig
from Grant Likely:
* add oneline description to header
* inline references to DRIVER_NAME
* inline references to BUSY_TIMEOUT
* open coded bytes_per_word()
* spi_readl/writel -> spi_tegra_readl/writel
* move transfer validation to spi_tegra_transfer
* don't request_mem_region iomem as platform bus does that for us
* __exit -> __devexit
v3 changes:
from Russell King:
* put request_mem_region back int
from Grant Likely:
* remove #undef DEBUG
* add SLINK_ to register bit defines
* remove unused bytes_per_word
* make spi_tegra_readl/writel static linine
* various refactoring for clarity
* mark err if BSY bit is not cleared after 1000 retries
* move spinlock to protect setting of RDY bit
* subsys_initcall -> module_init
v3 changes:
from Grant Likely:
* update spi_tegra to use PTR_ERRless dma API
Signed-off-by: Erik Gilling <konkers@android.com>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Russell King <linux@arm.linux.org.uk>
Colin Cross [Mon, 5 Apr 2010 20:16:42 +0000 (13:16 -0700)]
[ARM] tegra: Add APB DMA support
The APB DMA block handles DMA transfers to and from some peripherals
in the Tegra SOC. It reads from sequential addresses on the memory
bus, and writes repeatedly to the same address on the APB bus.
Two transfer modes are supported, oneshot for transferring a known
size to or from a peripheral, and continuous for streaming data.
In continuous mode, a callback occurs when the buffer is half full
to allow the existing data to be handled and a new request queued.x
v2 changes:
dma API no longer uses PTR_ERR
Signed-off-by: Erik Gilling <konkers@android.com>
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Thu, 11 Feb 2010 01:13:29 +0000 (17:13 -0800)]
[ARM] tegra: Add tegra_defconfig
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Erik Gilling <konkers@android.com>
Colin Cross [Fri, 23 Apr 2010 03:30:13 +0000 (20:30 -0700)]
[ARM] tegra: Add cpufreq support
Implement cpufreq support for the Tegra SOC. DVFS is handled by the
core virtual cpu clock. The frequencies of the two cores are tied
together, the highest frequency requested by either core determines
the actual frequency.
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 25 Jun 2010 01:57:00 +0000 (18:57 -0700)]
[ARM] tegra: common: Update common clock init table
Renames clocks in the clock init table to match the datasheet names
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Tue, 8 Jun 2010 03:49:46 +0000 (20:49 -0700)]
[ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups
- Add drivers to clock lookup table
- Add new pll_m entries
- Support I2C U16 divider
- Fix rate reporting on 32.768kHz clock
- Call propagate rate only if set_rate succeeds
- Add support for audio_sync clock
- Add 24MHz to PLLA frequency list
- Correct i2s1/2/spdifout mux
- Add suspend support
- Fix enable/disable parent clocks in set_parent
- Add max_rate parameter to all clocks
- DVFS support
- Add virtual cpu clock with dvfs
- Support clk_round_rate
- Fix requesting very high periph frequencies
- Add quirks for PLLU:
PLLU is slightly different from the rest of the PLLs. The
lock enable bit is at bit 22 instead of 18 in the MISC
register, and the post divider field is a single bit with
reversed values from other PLLs.
- Simplify recalculating clock rates
- Fix UART divider flags
- Remove unused clock ops
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 23 Jun 2010 22:49:17 +0000 (15:49 -0700)]
[ARM] tegra: Add support for reading fuses
The Tegra SOC contains fuses to identify the CPU type and
bin, and a unique id. The CPU info is required to determine
the correct voltages for each cpu and core frequency.
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 7 Apr 2010 19:59:42 +0000 (12:59 -0700)]
[ARM] tegra: gpio: Add suspend and wake support
Includes checkpatch fixes and TEGRA_NR_GPIOS changes from
Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Fri, 9 Jul 2010 22:13:52 +0000 (15:13 -0700)]
[ARM] tegra: pinmux: add safe values, move tegra2, add suspend
- the reset values for some pin groups in the tegra pin mux can result in
functional errors due to conflicting with actively-configured pin groups
muxing from the same controller. this change adds a known safe, non-
conflicting mux for every pin group, which can be used on platforms
where the pin group is not routed to any peripheral
- also add each pin group's I/O voltage rail, to enable platform code to
map from the pin groups used by each interface to the regulators used
for dynamic voltage control
- add routines to individually configure the tristate, pin mux and pull-
ups for a pingroup_config array, so that it is possible to program
individual values at run-time without modifying other values.
this allows driver power-management code to reprogram individual
interfaces into lower power states during idle / suspend, or to
reprogram the pin mux to support multiple physical busses per
internal controller (e.g., sharing a single I2C or SPI controller
across multiple pin groups)
- move chip-specific data like pingroups and drive-pingroups
out of the common code and into chip-specific code
- fix debug output for group with no pullups
- add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE
will automatically select a mux setting that is guaranteed not to
conflict with any of the hardware blocks.
Signed-off-by: Gary King <gking@nvidia.com>
Gary King [Tue, 6 Apr 2010 03:30:59 +0000 (20:30 -0700)]
[ARM] tegra: add suspend and mirror irqs to legacy controller
mirror IRQ enable and disable operations on the legacy PPI system
interrupt controller, since the legacy controller is responsible
for responding to wakeup interrupts when the CPU is in LP2 idle mode
save the irq controller state on suspend and restore on resume
Signed-off-by: Gary King <gking@nvidia.com>
Colin Cross [Mon, 5 Apr 2010 22:22:21 +0000 (15:22 -0700)]
[ARM] tegra: Add legacy irq support
The "legacy irq controller" duplicates the functionality of the GIC,
but remains powered during the cpu suspend and idle modes that power
down the CPU and the GIC.
Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 28 Jul 2010 04:34:38 +0000 (21:34 -0700)]
[ARM] tegra: update iomap
Add missing io address map entries from datasheet.
Add the IRAM area to the statically mapped io regions.
Correct the onewire, USB, and statmon addresses
Signed-off-by: Colin Cross <ccross@android.com>
Linus Torvalds [Wed, 29 Sep 2010 01:01:22 +0000 (18:01 -0700)]
Linux 2.6.36-rc6
David Howells [Wed, 29 Sep 2010 00:57:02 +0000 (01:57 +0100)]
MN10300: Handle missing sys_cacheflush() when caching disabled
When caching is disabled on the MN10300 arch, the sys_cacheflush()
function is removed by conditional stuff in the makefiles, but is still
referred to by the syscall table.
Provide a null version that just returns 0 when caching is disabled (or
-EINVAL if the arguments are silly).
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Tue, 28 Sep 2010 20:26:57 +0000 (13:26 -0700)]
alpha: fix compile problem in arch/alpha/kernel/signal.c
Tssk. Apparently Al hadn't checked commit
c52c2ddc1dfa ("alpha: switch
osf_sigprocmask() to use of sigprocmask()") at all. It doesn't compile.
Fixed as per suggestions from Michael Cree.
Reported-by: Michael Cree <mcree@orcon.net.nz>
Cc: Al Viro <viro@ftp.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Tue, 28 Sep 2010 19:38:52 +0000 (12:38 -0700)]
Merge branch 'upstream-linus' of git://git./linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
ahci: fix module refcount breakage introduced by libahci split
Tejun Heo [Tue, 21 Sep 2010 07:25:48 +0000 (09:25 +0200)]
ahci: fix module refcount breakage introduced by libahci split
libata depends on scsi_host_template for module reference counting and
sht's should be owned by each low level driver. During libahci split,
the sht was left with libahci.ko leaving the actual low level drivers
not reference counted. This made ahci and ahci_platform always
unloadable even while they're being actively used.
Fix it by defining AHCI_SHT() macro in ahci.h and defining a sht for
each low level ahci driver.
stable: only applicable to 2.6.35.
Signed-off-by: Tejun Heo <tj@kernel.org>
Reported-by: Pedro Francisco <pedrogfrancisco@gmail.com>
Tested-by: Michael Tokarev <mjt@tls.msk.ru>
Cc: stable@kernel.org
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Linus Torvalds [Tue, 28 Sep 2010 19:13:13 +0000 (12:13 -0700)]
Merge branch 'hwmon-for-linus' of git://git./linux/kernel/git/groeck/staging
* 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging:
hwmon (coretemp): Fix build breakage if SMP is undefined
Linus Torvalds [Tue, 28 Sep 2010 19:02:22 +0000 (12:02 -0700)]
Merge branch 'for-linus' of git://git./linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: fix pci_resource_alignment prototype
Linus Torvalds [Tue, 28 Sep 2010 19:01:26 +0000 (12:01 -0700)]
Merge git://git./linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (47 commits)
tcp: Fix >4GB writes on 64-bit.
net/9p: Mount only matching virtio channels
de2104x: fix ethtool
tproxy: check for transparent flag in ip_route_newports
ipv6: add IPv6 to neighbour table overflow warning
tcp: fix TSO FACK loss marking in tcp_mark_head_lost
3c59x: fix regression from patch "Add ethtool WOL support"
ipv6: add a missing unregister_pernet_subsys call
s390: use free_netdev(netdev) instead of kfree()
sgiseeq: use free_netdev(netdev) instead of kfree()
rionet: use free_netdev(netdev) instead of kfree()
ibm_newemac: use free_netdev(netdev) instead of kfree()
smsc911x: Add MODULE_ALIAS()
net: reset skb queue mapping when rx'ing over tunnel
br2684: fix scheduling while atomic
de2104x: fix TP link detection
de2104x: fix power management
de2104x: disable autonegotiation on broken hardware
net: fix a lockdep splat
e1000e: 82579 do not gate auto config of PHY by hardware during nominal use
...
Guenter Roeck [Tue, 28 Sep 2010 01:01:49 +0000 (18:01 -0700)]
hwmon (coretemp): Fix build breakage if SMP is undefined
Commit
e40cc4bdfd4b89813f072f72bd9c7055814d3f0f introduced
a build breakage if CONFIG_SMP is undefined. This commit
fixes the problem.
This fix is only a workaround. For a real fix, cpu_sibling_mask() should
be defined in UP include code, eg in linux/smp.h, and asm/smp.h should not be
included directly. This fix is currently not possible because asm/smp.h defines
cpu_sibling_mask() unconditionally and is included directly from many source
files.
Reported-by: Ingo Molnar <mingo@elte.hu>
Tested-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>