ReleaseNotes: Add info on PTX back-end

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156745 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon: Initialize TBB to 0.

Found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156744 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Xcode case (Upper X, lower c)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156743 91177308-0d34-0410-b5e6-96231b3b80d8

ReleaseNotes: Add a note about zero_undef on llvm.cttz/ctlz. Extend x86 section. Add a bullet for dwarf access tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156740 91177308-0d34-0410-b5e6-96231b3b80d8

ReleaseNotes: Add a blurb about llvm-mc -g and move inliner changes into the optimizer sections. Verbosify some bullets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156739 91177308-0d34-0410-b5e6-96231b3b80d8

ReleaseNotes: Document that LLVM was rewritten in python.

                            ^~~~
                            llvm-build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156738 91177308-0d34-0410-b5e6-96231b3b80d8

ReleaseNotes: Add bullets for removed targets. Extend the note about llvm-ld removal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156737 91177308-0d34-0410-b5e6-96231b3b80d8

Outline some clang 3.1 highlights off the top of my head.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156736 91177308-0d34-0410-b5e6-96231b3b80d8

Add a link for every project.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156735 91177308-0d34-0410-b5e6-96231b3b80d8

Add blurb for LLVM D Compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156733 91177308-0d34-0410-b5e6-96231b3b80d8

Add blurbs for pocl and TCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156732 91177308-0d34-0410-b5e6-96231b3b80d8

Add OSL blurb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156731 91177308-0d34-0410-b5e6-96231b3b80d8

Add FAUST blurb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156730 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the tool documentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156729 91177308-0d34-0410-b5e6-96231b3b80d8

Document Python bindings in release notes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156724 91177308-0d34-0410-b5e6-96231b3b80d8

Fix spacing after if.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156716 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the .rept directive. Patch by Vladmir Sorokin. I added support
for nesting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156714 91177308-0d34-0410-b5e6-96231b3b80d8

ELF: Add support for the asm .version directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156712 91177308-0d34-0410-b5e6-96231b3b80d8

AsmParser: Add support for the .purgem directive.

Based on a patch by Team PaX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156709 91177308-0d34-0410-b5e6-96231b3b80d8

AsmParser: Give a nice error message for .code16gcc, which is currently unsupported.

Patch by Team PaX!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156708 91177308-0d34-0410-b5e6-96231b3b80d8

AsmParser: ignore the .extern directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156707 91177308-0d34-0410-b5e6-96231b3b80d8

AsmParser: Add support for .ifc and .ifnc directives.

Based on a patch from PaX Team.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156706 91177308-0d34-0410-b5e6-96231b3b80d8

AsmParser: Add support for .ifb and .ifnb directives.

Based on a patch from PaX Team.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156705 91177308-0d34-0410-b5e6-96231b3b80d8

Recommited r156374 with critical fixes in BitcodeReader/Writer:
Ordinary patch for PR1255.
Added new case-ranges orientated methods for adding/removing cases in SwitchInst. After this patch cases will internally representated as ConstantArray-s instead of ConstantInt, externally cases wrapped within the ConstantRangesSet object.
Old methods of SwitchInst are also works well, but marked as deprecated. So on this stage we have no side effects except that I added support for case ranges in BitcodeReader/Writer, of course test for Bitcode is also added. Old "switch" format is also supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156704 91177308-0d34-0410-b5e6-96231b3b80d8

Teach Function::hasAddressTaken that BlockAddress doesn't really take
the address of a function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156703 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure new value jump is enabled for Hexagon V5 as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156700 91177308-0d34-0410-b5e6-96231b3b80d8

Support for Hexagon feature, New Value Jump.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156698 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156697 91177308-0d34-0410-b5e6-96231b3b80d8

Remove MipsEmitGPRestore.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156696 91177308-0d34-0410-b5e6-96231b3b80d8

Delete all functions that are no longer needed in MipsFunctionInfo, including
the ones that get or set the frame index for the $gp save slot.

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156695 91177308-0d34-0410-b5e6-96231b3b80d8

Stop reserving register $gp. Do not call isGPFI to check whether a frame object
is the $gp save slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156694 91177308-0d34-0410-b5e6-96231b3b80d8

Do not add the pass which restores $gp after every function call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156693 91177308-0d34-0410-b5e6-96231b3b80d8

Make the following changes in MipsISelLowering.cpp:

- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8

Make the following changes in MipsFrameLowering.cpp:

- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156691 91177308-0d34-0410-b5e6-96231b3b80d8

Speed up computeComposites() by using the new SubReg -> SubIdx map.

TableGen doesn't need to search through the SubRegs map to find an
inverse entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156690 91177308-0d34-0410-b5e6-96231b3b80d8

Make the following changes in MipsAsmPrinter.cpp:

- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8

Hoist simpler checks above llvm::PointerMayBeCaptured. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156687 91177308-0d34-0410-b5e6-96231b3b80d8

Don't look for empty live ranges in the unions.

Empty live ranges represent undef and still get allocated, but they
won't appear in LiveIntervalUnions.

Patch by Patrik Hägglund!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156685 91177308-0d34-0410-b5e6-96231b3b80d8

Insert instructions to the entry basic block which initializes the global
pointer register.

This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8

Add doxygen comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156665 91177308-0d34-0410-b5e6-96231b3b80d8

Do not replace operands of pseudo instructions with register $zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8

Revert 156658.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156662 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Fast-isel doesn't use the expect intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156658 91177308-0d34-0410-b5e6-96231b3b80d8

Use regular expression to match register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156656 91177308-0d34-0410-b5e6-96231b3b80d8

Make the URL a link instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156655 91177308-0d34-0410-b5e6-96231b3b80d8

[Support/StringRef] Add find_last_not_of and {r,l,}trim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156652 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extraneous ; and the resulting warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156649 91177308-0d34-0410-b5e6-96231b3b80d8

Add mention of Glasgow Haskell Compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156648 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Add support for selecting @llvm.trap().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8

Updated instruction table due to addded intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156644 91177308-0d34-0410-b5e6-96231b3b80d8

Remove warnings from HexagonVLIWPacketizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156636 91177308-0d34-0410-b5e6-96231b3b80d8

Some release notes for dragonegg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156635 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon constant extender support.

Patch by Jyotsna Verma.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8

Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices.  Minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 intrinsics support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8

Defer computation of SuperRegs.

Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8

objectsize: add a few more tests and fix a bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156625 91177308-0d34-0410-b5e6-96231b3b80d8

[fast-isel] Rather then assert (or segfault in a non-asserts build), fall back
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8

The return type is an unsigned, not a bool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8

Add space before an open parenthesis in control flow statements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8

Added X86 Atom latencies to X86InstrMMX.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8

PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156613 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test/CodeGen/X86/tls-pie.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156612 91177308-0d34-0410-b5e6-96231b3b80d8

Implement initial-exec TLS model for 32-bit PIC x86

This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8

Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a use after free when the streamer is destroyed. Fixes pr12622.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156606 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a misleading comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156602 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156601 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a minor logic mistake transforming compares in instcombine.  PR12514.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156600 91177308-0d34-0410-b5e6-96231b3b80d8

ARM: peephole optimization to remove cmp instruction

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8

Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8

Allow unique_file to take a mode for file permissions, but default
to user only read/write.

Part of rdar://11325849

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156591 91177308-0d34-0410-b5e6-96231b3b80d8

Fix intendation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156589 91177308-0d34-0410-b5e6-96231b3b80d8

Compute secondary sub-registers.

The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8

objectsize: add support for GEPs with non-constant indexes
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8

Added X86 Atom latencies for instructions in X86InstrInfo.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for the 'X' inline asm operand modifier.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Print machineinstrs with -debug-only=misched

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8

misched: tracing register pressure heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Add register pressure backoff to ConvergingScheduler.

Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Release only unscheduled nodes into ReadyQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Added ReadyQ container wrapper for Top and Bottom Queues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8

misched: Introducing Top and Bottom register pressure trackers during scheduling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 Support - V5 td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8

Hexagon V5 FP Support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8

RegPressure: API for speculatively checking instruction pressure.

Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the
tracker by speculatively handling an instruction out of order. But it
is convenient for now. In the future, we will cache each instruction's
pressure contribution to make this efficient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8

RegPressure: fix array index iteration style.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8

Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156558 91177308-0d34-0410-b5e6-96231b3b80d8

Revert: 156550 "ARM: peephole optimization to remove cmp instruction"

This commit broke an external linux bot and gave a compile-time warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8

Precompute lists of explicit sub-registers and indices.

The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8

Rewrite ScalarEvolution::hasOperand to use an explicit worklist instead
of recursion, to avoid excessive stack usage on deep expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156554 91177308-0d34-0410-b5e6-96231b3b80d8

teach DSE and isInstructionTriviallyDead() about calloc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156553 91177308-0d34-0410-b5e6-96231b3b80d8

formatting change: strip debug info from test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156551 91177308-0d34-0410-b5e6-96231b3b80d8

ARM: peephole optimization to remove cmp instruction

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem with incomplete equality testing of PHINodes in
Instruction::IsIdenticalToWhenDefined.

This manifested itself when inlining two calls to the same function.  The
inlined function had a switch statement that returned one of a set of
global variables.  Without this modification, the two phi instructions that
chose values from the branches of the switch instruction inlined from the
callee were considered equivalent and jump-threading replaced a load for the
first switch value with a phi selecting from the second switch, thereby
producing incorrect code.

This patch has been tested with "make check-all", "lnt runteste nt", and
llvm self-hosted, and on the original program that had this problem,
wireshark.

<rdar://problem/11025519>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156548 91177308-0d34-0410-b5e6-96231b3b80d8

Fix merge-typo and cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8