Don't back past debug info intrinsics; SCEVExpander's strategy
for ignoring debug info intrinsics everywhere else is to advance
past them, and it needs to be consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99332 91177308-0d34-0410-b5e6-96231b3b80d8

fix an infinite loop in Module::getEndianness, PR6684
patch by Alex Mac!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99330 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in the comment for N3VX class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8

Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8

Add New NEON Format NVdVmVCVTFrm.
Converted some of the NEON vcvt instructions to this format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8

Skip debugging intrinsics when sinking unused invariants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99324 91177308-0d34-0410-b5e6-96231b3b80d8

Add New NEON Format NVdVmImmFrm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8

Ignore dbg_value's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99321 91177308-0d34-0410-b5e6-96231b3b80d8

Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99320 91177308-0d34-0410-b5e6-96231b3b80d8

Code clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99319 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for llvm-gcc r99305.  Radar 7659636.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99306 91177308-0d34-0410-b5e6-96231b3b80d8

Fix bad indentation, 80-column violations, and trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8

Add New NEON Format NVdImmFrm.
Ref: A7.4.6 One register and a modified immediate value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8

Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99284 91177308-0d34-0410-b5e6-96231b3b80d8

Forgot this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99283 91177308-0d34-0410-b5e6-96231b3b80d8

Teach simplify libcall to transform __strcpy_chk to __memcpy_chk to enable optimizations down stream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99282 91177308-0d34-0410-b5e6-96231b3b80d8

add assert in argpromotion, which cannot trigger
if Function::hasAddressTaken works as advertised

also included some cosmetic cleanups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99276 91177308-0d34-0410-b5e6-96231b3b80d8

word-o

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99275 91177308-0d34-0410-b5e6-96231b3b80d8

Rename some instructions to match the corresponding NEON opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8

Change VST1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an incorrect logic causing instcombine to miss some _chk -> non-chk transformations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99263 91177308-0d34-0410-b5e6-96231b3b80d8

Change VLD1 instructions for loading Q register values to operate on pairs
of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Switch to using MCInst fragments to do relaxation.

Also, both MCMachOStreamer and MCAssembler are now target independent!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99256 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99249 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99248 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99245 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Tweak MCInstFragment to include the encoded data and fixups, so that we don't need to recompute them during relaxation. I will revisit this once all the other pieces of fast relaxation are in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99244 91177308-0d34-0410-b5e6-96231b3b80d8

Put MCSectionCOFF::Name into the MCContext instead of leaking it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99231 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Add MCInstFragment, not used yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99229 91177308-0d34-0410-b5e6-96231b3b80d8

Add a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99228 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR6673: updating the callback should not clear the map.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99227 91177308-0d34-0410-b5e6-96231b3b80d8

Emit DW_AT_low_pc and DW_AT_high_pc attributes for TAG_compile_unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99225 91177308-0d34-0410-b5e6-96231b3b80d8

Fix 80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99224 91177308-0d34-0410-b5e6-96231b3b80d8

DW_AT_stmt_list attribute attached with a compile unit encodes offset of line number information for this compile unit in debug_line section. This offset is always zero when only one compile unit is emitted in a object file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99223 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Fix a few more cases we were passing an MCDataFragment when a MCFragment would do, and sprinkle in some const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99218 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99217 91177308-0d34-0410-b5e6-96231b3b80d8

MCInst: Add ::dump_pretty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99216 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99214 91177308-0d34-0410-b5e6-96231b3b80d8

Change intrinsic result type for void to store it as an empty list
instead of as a single element list with VoidTy.  Now with a fix
for the verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Change MCObjectWriter::RecordRelocation to take an MCFragment (instead of a MCDataFragment). Object files should only need the generic MCFragment features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99205 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O: Factor out getOrCreateDataFragment().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99204 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Eliminate MCFragment::getMaxFileSize.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99203 91177308-0d34-0410-b5e6-96231b3b80d8

MC: Share the MCAsmLayout object, although its still not used for anything important.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99202 91177308-0d34-0410-b5e6-96231b3b80d8

Rename one more NEON instruction that I missed earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a memory leak from DIE::addSiblingOffset() by adding the DIEValue
it allocates to DwarfDebug::DIEValues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99196 91177308-0d34-0410-b5e6-96231b3b80d8

80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99195 91177308-0d34-0410-b5e6-96231b3b80d8

Regroup some instructions.  No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8

Rename some VLD1/VST1 instructions to match the implementation, i.e., the
corresponding NEON instructions, instead of operation they are currently
used for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some redundant instruction classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8

llc doesn't need LinkAllVMCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99186 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
specify encoding bits in arguments instead of "let" expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8

Completely remove Blackfin patterns that thought JustCC was i1.

Thanks, Chris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99183 91177308-0d34-0410-b5e6-96231b3b80d8

Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid leaking the FunctionPassManager from opt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99180 91177308-0d34-0410-b5e6-96231b3b80d8

backing out r99170 because it still fails on clang-x86_64-darwin10-fnt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99171 91177308-0d34-0410-b5e6-96231b3b80d8

Now that hopefully all direct accesses to InvokeInst operands are fixed
we can reapply the InvokeInst operand reordering patch. (see r98957).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99170 91177308-0d34-0410-b5e6-96231b3b80d8

Free all Constants in ~LLVMConstantImpl.  We avoid assertion failures
by dropping all references from all constants that can use other
constants before trying to destroy any of them.

I also had to free bugpoint's Module in ~BugDriver().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99160 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the ocaml kaleidoscope tutorial to fix linking external libraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99151 91177308-0d34-0410-b5e6-96231b3b80d8

modernize the do-all-for-me target to run lit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99148 91177308-0d34-0410-b5e6-96231b3b80d8

Re-add the Metadata.h include to LLVMContextImpl.h so that MDNode is complete
where FoldingSet<MDNode> is instantiated.  Clang and MSVC complain; gcc
doesn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99147 91177308-0d34-0410-b5e6-96231b3b80d8

Move the LLVMContextImpl implementation into a .cpp file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99146 91177308-0d34-0410-b5e6-96231b3b80d8

Memoize InlineAsms into the LLVMContext and delete them on shutdown.
Fixes PR803.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99143 91177308-0d34-0410-b5e6-96231b3b80d8

XFAIL tests from LLVMC on valgrind or valgrind+leak-checking.  We
don't care about leaks from tblgen, and I assume we don't care about
valgrind errors in llvm-gcc/g++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99115 91177308-0d34-0410-b5e6-96231b3b80d8

Free SavedLI even if SimpleRegisterCoalescing::JoinCopy() returns early.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99113 91177308-0d34-0410-b5e6-96231b3b80d8

When we don't pass --vg-leak to lit, pass --leak-check=no to valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99112 91177308-0d34-0410-b5e6-96231b3b80d8

Fix suggested parentheses warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99111 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for XFAILing valgrind runs with memory leak checking independently
of runs without leak checking.  We add -vg to the triple for non-checked runs,
or -vg_leak for checked runs.  Also use this to XFAIL the TableGen tests, since
tablegen leaks like a sieve.  This includes some valgrindArgs refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99103 91177308-0d34-0410-b5e6-96231b3b80d8

MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99102 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc: Fix MCInstPrinter memory leaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99101 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O: Remove Darwin host specific tests, we don't need them anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99100 91177308-0d34-0410-b5e6-96231b3b80d8

MC/Mach-O: Tweak optimal_nop test to be host independent.
 - This also avoids us running valgrind on /usr/bin/as, which has leaks. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99099 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc: Fix memory leak of MCAsmInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99098 91177308-0d34-0410-b5e6-96231b3b80d8

TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8

pr6652: Use LDM to restore PC to the return address on ARMv4.
Patch by John Tytgat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8

Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8

Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
address register writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8

Add variants of VST2, VST3 and VST4 with address register writeback, and
rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8

Add instructions for double-spaced VST3 and VST4 without address register
writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8

tests: Mangle '-vg' onto the end of the triple when running under valgrind, so
we can use the standard XFAIL and XTARGET to conditional tests based on
valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99088 91177308-0d34-0410-b5e6-96231b3b80d8

Add a setCalledFunction member to InvokeInst (like in CallInst)
and use this (as well as getCalledValue) to access the callee,
instead of {g|s}etOperand(0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99084 91177308-0d34-0410-b5e6-96231b3b80d8

Add VST1 instructions with address register writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8

Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
address register writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy some more comments and whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8

Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy some comments and whitespace for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8

Rename some instructions for consistency and sanity: use "_UPD" suffix for
load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8

Add instructions for double-spaced VLD3 and VLD4 without address register
writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8

Add VLD1 instructions with address register writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8

PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99061 91177308-0d34-0410-b5e6-96231b3b80d8

Revert the rest of 98679.
--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a very bad typo.  Since the register number was off by one, the ARM
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8

Clear the SCEVExpander's insertion point after making deletions,
so that the SCEVExpander doesn't retain a dangling pointer as its
insert position. The dangling pointer in this case wasn't ever used
to insert new instructions, but it was causing trouble with
SCEVExpander's code for automatically advancing its insert position
past debug intrinsics.

This fixes use-after-free errors that valgrind noticed in
test/Transforms/IndVarSimplify/2007-06-06-DeleteDanglesPtr.ll and
test/Transforms/IndVarSimplify/exit_value_tests.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99036 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid svn. Add back to the lost sibcall tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99033 91177308-0d34-0410-b5e6-96231b3b80d8

If call result is in ST0 and it is not being passed to the caller's
caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8

Better fix for r98994, MachObjectWriterImpl wasn't intended to be virtual.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99031 91177308-0d34-0410-b5e6-96231b3b80d8

Add NLdStFrm Format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r98679.  The disassembler will be updated to depend on the existence of
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r99009 temporarily it seems to be breaking the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8

Revert this change, since it was causing ARM performance regressions.

--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8