arm64: dts: rk3328-evb: enable hdmi audio

Change-Id: Ic67744ac5554b90b6d9f85eeedf4721562f8155f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

phy: rockchip-inno-usb2: fix some race conditions

There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.

Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.

Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.

CPU 0:
- rockchip_usb2phy_bvalid_irq()
 - rockchip_usb2phy_otg_sm_work()
  - detect connect to PC usb, do phy power on
   - rockchip_usb2phy_power_on()

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - rockchip_usb2phy_power_on()

Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.

Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.

The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.

CPU 0:
- rockchip_chg_detect_work()
 - power off phy and start to do charge detection work

CPU 1:
- dwc3 driver do runtime resume process
 - dwc3_runtime_resume()
  - dwc3_core_init()
   - phy_power_on()
    - power on phy again

This race condition may cause charger detection and later usb
enumeration abnormally.

Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.

This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.

Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>

Revert "drm/rockchip: vop: round_up pitches to word align"

This reverts commit 7e705c4974eaa8abaf44cb1542d3ec49d520fde8.

Change-Id: I498ade43de012f65ea39624bd2982b4a84bcbf54
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: round_up pitches to word align

Change-Id: I836193ca37fb62c72c61aa47a807959c3c189925
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: logo: use unique plane property logo mirror

The logo framework use state->rotation may conflict to common drm
update, cause display abnormal

Change-Id: I09b6b898a7606cd05371af1f4b25254945923d0d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: clk: rockchip: mark some special clk as critical on rk3368

The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 223c24be740d293519ef8e03f5c075fab5512fd2)

Conflicts:
drivers/clk/rockchip/clk-rk3368.c

Change-Id: I31c1c7efb7a83652501a7f53ff5931d9f308f736
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3288

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 55bb6a633c33caf68ab470907ecf945289cb733d)

Conflicts:
drivers/clk/rockchip/clk-rk3288.c

Change-Id: I6271a903deb9ca21b5e74fd2c1ad4cf69f7021e1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036

No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f2893aaba435fcb55b86dc1be8c6f64f8d60e64b)

Change-Id: I3cd9578f73a69eb0f09d1f40c22ee55b393149aa
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f8ba2d68e54fbca340ad0fce97397291ba9637bc)

Change-Id: Ia8683d7b49523284043457727665d7e58d1551ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add "," to mux_pll_src_apll_dpll_gpll_usb480m_p on rk3036

The mux_pll_src_apll_dpll_gpll_usb480m_p parent list was missing a ","
between the 3rd and 4th parent names, making them fall together and thus
lookups fail. Fix that.

Fixes: 5190c08b2989 ("clk: rockchip: add clock controller for rk3036")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit 9b1b23f03abdd25ffde8bbfe5824b89bc0448c28)

Change-Id: I535b64fc7c902a4e9c64b4b803bb03126b7ba110
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: mark noc and some special clk as critical on rk3228

The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f18c0994cda54dc21d3b0ce2ba130b5ea8f58666)

Conflicts:
drivers/clk/rockchip/clk-rk3228.c

Change-Id: Ie2c4c8d2c73a62efe96e64a3ec638970e82051d1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: rockchip_defconfig: support dtb appended and bootargs extended

This patch support using appended device tree blob to zImage and
supplementing the appended DTB with traditional ATAG information.

Change-Id: I8e8e63513c17544fdafd9107fda425740c63220e
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

rk: gcc-wrapper.py ignore atags_to_fdt.c:98

Change-Id: Ie7d1c5b7ba5d1147c1996d73f19d5e0d768998ec
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

UPSTREAM: ARM: 8500/1: fix atags_to_fdt with stack-protector-strong

Building with CONFIG_CC_STACKPROTECTOR_STRONG triggers protection code
generation under CONFIG_ARM_ATAG_DTB_COMPAT but this is too early for
being able to use any of the stack_chk code. Explicitly disable it for
only the atags_to_fdt bits.

Change-Id: Ib1f66cc4083b4f04d713c3c70610b8a337a6b0ff
Suggested-by: zhxihu <zhxihu@marvell.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 7f66cd3f5420e7d11abd234033e7cb7a9738fc38)

UPSTREAM: clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f6022e88faca1a6a21cbd0f009b477bc530b9cc7)

Change-Id: Ib933e398bc8e40d8659bc1cdc419116f48f6ae30
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: clk: rockchip: add dt-binding header for rk3128

Add the dt-bindings header for the rk3128,
that gets shared between the clock controller and
the clock references in the dts.
Add softreset ID for rk3128.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit b20841b9e0d730206de6ee95f4d00e3f8815ad50)

Change-Id: I70c055570319abe4547ac2a42b9139c7248abb13
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

UPSTREAM: dt-bindings: add bindings for rk3128 clock controller

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit de2ddc3b694d4594d922534db19e15fc39a3fcee)

Change-Id: I7ee66379d024020a9f8bcc98c3d9c4341391cccd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

OP-TEE: fix warning when LPAE is activated on ARM

When LPAE is activated, the dma_addr_t type is u64,
but pointer is still 32bit on arm32 platform.
1. %pad is used to print dma_addr_t type in log.
2. The member paddr(dma_addr_t type) in struct shm is cast
to unsigned long when it needs to be cast to a pointer. The cast
is fine as the value of paddr in struct shm is always less than 4G.

Change-Id: I1e2112796f657759dfa845258ea19558cb84c4ec
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

fiq debugger: rockchip: fix crash because of invalid sp_el0

(1) use cpu id from bl31 delivers;
(2) sp_el0 should point to kernel address in EL1 mode.

On ARM64, kernel uses sp_el0 to store current_thread_info(),
we see a problem: when fiq occurs, cpu is EL1 mode but sp_el0
point to userspace address. At this moment, if we read
'current_thread_info()->cpu' or other, it leads an error.

We find above situation happens when save/restore cpu context
between system mode and user mode under heavy load.
Like 'ret_fast_syscall()', kernel restore context of user mode,
but fiq occurs before the instruction 'eret', so this causes the
above situation.

Assembly code:

ffffff80080826c8 <ret_fast_syscall>:

...skipping...

ffffff80080826fc:       d503201f        nop
ffffff8008082700:       d5384100        mrs     x0, sp_el0
ffffff8008082704:       f9400c00        ldr     x0, [x0,#24]
ffffff8008082708:       d5182000        msr     ttbr0_el1, x0
ffffff800808270c:       d5033fdf        isb
ffffff8008082710:       f9407ff7        ldr     x23, [sp,#248]
ffffff8008082714:       d5184117        msr     sp_el0, x23
ffffff8008082718:       d503201f        nop
ffffff800808271c:       d503201f        nop
ffffff8008082720:       d5184035        msr     elr_el1, x21
ffffff8008082724:       d5184016        msr     spsr_el1, x22
ffffff8008082728:       a94007e0        ldp     x0, x1, [sp]
ffffff800808272c:       a9410fe2        ldp     x2, x3, [sp,#16]
ffffff8008082730:       a94217e4        ldp     x4, x5, [sp,#32]
ffffff8008082734:       a9431fe6        ldp     x6, x7, [sp,#48]
ffffff8008082738:       a94427e8        ldp     x8, x9, [sp,#64]
ffffff800808273c:       a9452fea        ldp     x10, x11, [sp,#80]
ffffff8008082740:       a94637ec        ldp     x12, x13, [sp,#96]
ffffff8008082744:       a9473fee        ldp     x14, x15, [sp,#112]
ffffff8008082748:       a94847f0        ldp     x16, x17, [sp,#128]
ffffff800808274c:       a9494ff2        ldp     x18, x19, [sp,#144]
ffffff8008082750:       a94a57f4        ldp     x20, x21, [sp,#160]
ffffff8008082754:       a94b5ff6        ldp     x22, x23, [sp,#176]
ffffff8008082758:       a94c67f8        ldp     x24, x25, [sp,#192]
ffffff800808275c:       a94d6ffa        ldp     x26, x27, [sp,#208]
ffffff8008082760:       a94e77fc        ldp     x28, x29, [sp,#224]
ffffff8008082764:       f9407bfe        ldr     x30, [sp,#240]
ffffff8008082768:       9104c3ff        add     sp, sp, #0x130
ffffff800808276c:       d69f03e0        eret

Change-Id: I071e899f8a407764e166ca0403199c9d87d6ce78
Signed-off-by: chenjh <chenjh@rock-chips.com>

firmware: rockchip: use sp_el1 from bl31 delivers

we think 'if (fiq_pt_regs.pstate & 0x10)' doesn't make any
sense, use sp_el1 from bl31 delivers is ok.

Change-Id: I0792d76e39912b4ca5484b029761daac05cd719b
Signed-off-by: chenjh <chenjh@rock-chips.com>

ARM64: dts: rk3328-evb: enable hdmi

Change-Id: I42b74009d0ddded9afc10b24e453ca26808bd18e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rk3328: add hdmi display node

Change-Id: Ie4821b0c5e49c7b4ee083a2250a71f8ee3edb4e1
Signed-off-by: xuhuicong <xhc@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

arm64: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I9fc62405d5fad1979d35ada78249a388b0a547dd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_linux_defconfig: update by savedefconfig

Change-Id: I2b1de1cd8ee600e593d41cdad0516703d6c94558
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip_defconfig: update by savedefconfig

Change-Id: I5503f37643bd7b9cd0b80a3afbd9e0293608d0cd
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

arm64: rockchip_defconfig: update by savedefconfig

ROCKCHIP_CPUINFO is default y now.

Change-Id: I4d56e98265ceac3dc071c440a61fbffc736120c6
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm/rockchip: hdmi: support RK3328

Change-Id: I7d93f0d494f6824b0b6e2f82c2c1a57342ea551e
Signed-off-by: Hans Yang <yhx@rock-chips.com>
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

clk: rockchip: rk3328: add more flags for dclk_lcdc

Add CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT
for dclk_lcdc.

Change-Id: I19a4a8e5f9e2cc5fda8b70f1b632dccd538e02a0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

ARM64: dts: rockchip: add cpu version in cpuinfo for rk3328

Change-Id: Ief9dd80db35b7b55285b6773f270893a66da5f9d
Signed-off-by: Liang Chen <cl@rock-chips.com>

soc: rockchip: cpuinfo: read cpu version from eFuse

Change-Id: Ia18ff4e745f09fa04690bb7bc6d95169c389b9d2
Signed-off-by: Liang Chen <cl@rock-chips.com>

optee: fix mutex_unlock after mutex_lock

Change-Id: Ic5a4b5b4691b11083e5fd9e327fc4be82d626bfb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>

drm: bridge: dw-hdmi: fixup kernel crash when reboot with hdmi connected

when other devices bind failed,drm will unbind and re-bind all devices.
if don't cancel the delayed work but flush and destroy workqueue directly,
kernel point is likely to become NULL.

Change-Id: Ib48704186ee298cbd4daac1cdbbac5fb3906b6bb
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

usb: dwc_otg_310: pcd: fix force device mode issue

When tested usb device through force device mode method,
we found that usb device failed to connect to usb host
in the following case.

1. Use micro usb 2.0 OTG interface.
2. Plug in otg cable, and the id pin was pulled down
   to Ground.
3. User space force usb to enter device mode through
   'echo 2 > /sys/bus/platform/drivers/usb20_otg/force_usb_mode'
4. Use usb 2.0 Standard-A to Standard-A cable assembly,
   plug into otg cable receptor on one side, and connect
   to PC on the other side.
5. PC fail to enumerate our device, because of usb driver
   logical issue.

This is because that the dwc_otg_pcd_check_vbus_work()
only enable usb to start connecting if check the bvalid
and iddig is high. But in the above test case, the iddig
is low, so fail to start connection work. In this patch,
we enable usb to connect if iddig is high or usb is in
force device mode.

In addition, fix some coding style to increase the readability.

Change-Id: I08f1a4e6e7e5fb246b1716a20d4572d8b866f238
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: rockchip: select ARCH_DMA_ADDR_T_64BIT for LPAE

Rockchip RK3288 has some 64-bit capable DMA and therefore needs
dma_addr_t to be a 64-bit size. One user is the Mali GPU.

Change-Id: I47335415fb101b377c408a2631ce211cb3ae3bd8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

ARM: rockchip: enable ZONE_DMA for non 64-bit capable peripherals

Most IP cores on ARM Rockchip platforms can only address 32 bits of
physical memory for DMA. Thus ZONE_DMA should be enabled when LPAE
is activated.

Change-Id: I3fce3e01ba31270f066f49bc14fc2078c70d83ea
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

usb: dwc_otg_310: fix compile warning

When build with CONFIG_ARCH_DMA_ADDR_T_64BIT enabled:
drivers/usb/dwc_otg_310/dwc_otg_hcd.c: In function 'assign_and_init_hc':
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1093:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1131:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1161:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd.c:1189:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c: In function 'init_non_isoc_dma_desc':
drivers/usb/dwc_otg_310/dwc_otg_hcd_ddma.c:632:8: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c: In function 'handle_hc_ahberr_intr':
drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c:1699:14: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Change-Id: I4159d1d66ce24c97cc8085ee6e0fc4abde8c7423
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit b001ce5aa46de28c1f52c82d1e3c111e172bd5e4)
(cherry picked from commit 4952c8819aa0f0902ae620bf5de18f7a19f85e17)

dmaengine: pl330: make transfer run infinitely without CPU intervention

this patch is based on "https://patchwork.kernel.org/patch/8349321/"

Change-Id: I377d1590186ce6e17983b931ad035d58a9e69e85
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

drm/rockchip: Don't r-b swap for 32bit logo

Change-Id: Id664731fc92fe4b770b49b4c2772e14bdf276cf2
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm/rockchip: vop: round_up pitches to word align

VOP pitch register is word align, need align to word.

VOP_WIN0_VIR:
  bit[31:16] win0_vir_stride_uv
    Number of words of Win0 uv Virtual width
  bit[15:0] win0_vir_width
    Number of words of Win0 yrgb Virtual width
    ARGB888 : win0_vir_width
    RGB888 : (win0_vir_width*3/4) + (win0_vir_width%3)
    RGB565 : ceil(win0_vir_width/2)
    YUV : ceil(win0_vir_width/4)

Change-Id: I89a74fae725e88cf618c5b02c45538419feba28f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3399

There are 2 IP blocks pin routes need to be switched, that are
uart2dbg, pcie_clkreq.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit accc1ce7d2ffc6419a8eaf8c0190d9240df0c43f)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I940fbec4869f1395e66c8e693b838f58aa84a7a1

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3328

There are 8 IP blocks pin routes need to be switched, that are
uart2dbg, gmac-m1-optimized, pdm, spi, i2s2, card, tsp, cif.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit cedc964a59d48c793ddc0884b2f72a68fc234ae4)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I48fb4e8aa73930068b9ff6e8e547db267534b04d

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support for rk3228

There are 9 IP blocks pin routes need to be switched, that are
pwm-0, pwm-1, pwm-2, pwm-3, sdio, spi, emmc, uart2, uart1.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit d4970ee076f9aed396c322b41f56443a617116df)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9e4fbfb22f37add2ba5941b2b2ae9e55ed2d28b8

UPSTREAM: pinctrl: rockchip: Add iomux-route switching support

On the some rockchip SOCS, some things like rk3399 specific uart2 can use
multiple pins. Somewhere between the pin io-cells and the uart it seems
to have some sort of switch to decide to which pin to actually route the
data.

+-------+    +--------+  /- GPIO4_B0 (pinmux 2)

| uart2 | -- | switch | --- GPIO4_C0 (pinmux 2)

+-------+    +--------+  \- GPIO4_C3 (pinmux 2)
(switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1])

The routing switch is determined by one pin of a specific group to be set
to its special pinmux function. If the pinmux setting is wrong for that
pin the ip block won't work correctly anyway.

Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
 commit bd35b9bf8284338db35b3ff0d391b95d67b90444)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4de8dbe8a9183dd866b7dd8289f00c6e14f83dac

UPSTREAM: pinctrl: rockchip: avoid hardirq-unsafe functions in irq_chip

With real-time preemption, regmap functions cannot be used in the
implementation of irq_chip since they use spinlocks which may sleep.

Move the setting of the mux for IRQs to an irq_bus_sync_unlock handler
where we are allowed to sleep.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 88bb94216f59e10802aaf78c858a4146085faf18)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I94ae59be60c34022fdfdf67cd5b3059d852a5969

UPSTREAM: pinctrl: rockchip: split out verification of mux settings

We need to avoid calling regmap functions from irq handlers, so the next
commit is going to move the call to rockchip_set_mux() into an
irq_bus_sync_unlock handler.  But we can't return an error from there so
we still need to check the settings from rockchip_irq_set_type() and we
will use this new rockchip_verify_mux() function from there.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from git.kernel.org thierry.reding/linux-pwm.git for-next
 commit 05709c3e88f5f0adb7889facbfd546c998f65d59)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I421f9c2faf835ca821c574602d6b4a66cdde9769

UPSTREAM: pinctrl: rockchip: convert to raw spinlock

This lock is used from rockchip_irq_set_type() which is part of the
irq_chip implementation and thus must use raw_spinlock_t as documented
in Documentation/gpio/driver.txt.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: David Wu <david.wu@rock-chips.com>
(cherry picked from commit 70b7aa7a87b4593f50f634dc721e18bd1f9e5448)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I039ee4067832026f564989a05503e7507d178ee1

UPSTREAM: pinctrl: rockchip: remove unnecessary locking

regmap_update_bits does its own locking and everything else accessed
here is a local variable so there is no need to lock around it.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit f07bedc37f3cfb7b182e1337fe7c8acce71e3a25)

Change-Id: Id15c7ed10f32202c986c951ef328a84be5798af4
Signed-off-by: David Wu <david.wu@rock-chips.com>

UPSTREAM: pinctrl: rockchip: Add input schmitt support for rk3328

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from git.kernel.org thierry.reding/linux-pwm.git for-next
 commit 728d3f5afd991a44b4ec9d019d8556d8cb68db3f)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I15202d4fdd2fc35906d25e04cee63109d872405d

UPSTREAM: pinctrl: rockchip: Add input schmitt support

To prevent external signal crosstalk, some pins need to
enable input schmitt, like i2c pins, 32k-input pin and so on.

Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit e3b357d7dfe6b38a6064562bacf5c912b3443ac0)

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I2465e9df8abab3d8f46924e76a9084cda76a5a85

pinctrl: rockchip: sync with upstream for iomux recalculation

Change-Id: I795e2490e88203e8fb3d457cf293d70e34ab47e0
Signed-off-by: David Wu <david.wu@rock-chips.com>

optee: add res of cpumask_to_cpu0 and restore

if res is error,break;

Change-Id: I4c8a11ae02fef2aa30849a94afcce3af5569bbeb
Signed-off-by: sean.huang <sean.huang@rock-chips.com>
(cherry picked from commit 36bc4c52281bb9f476dc22f8bbd6e35183fa7863)
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

camera: rockchip: camsys driver v0.0x22.0

delete node in irqpool list when thread disconnect

Change-Id: I5602e138ab9bce751e24f6dc0a0f7348755be97a
Signed-off-by: zhangyunlong <dalon.zhang@rock-chips.com>

ARM: dts: phycore-rk3288: update

Change-Id: I4aa3ffd456040c9787871096b3483995be701da5
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Check if the phy is in an internal testing mode

The DP83867 seems to be always in an internal mode on our Board.
This mode can cause connection problems. We disable this mode.

Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved.
If Bit 7 is set, phy is in the internal testing mode.

Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Disable FORCE_LINK_GOOD in PHYCTRL

With FORCE_LINK_GOOD we are not able to get a link.
According to the TRM this bit should be 0 (Normal operation) in default.

Set FORCE_LINK_GOOD to default.

Change-Id: Iaa30bef20fc6f8313c018d18646879f62db49004
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Add documentation for CLK_OUT pin muxing

Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.

Change-Id: I5d341cac64581cd39ced0703054a70fd1eacc4a6
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

BACKPORT: net: phy: dp83867: allow RGMII_TXID/RGMII_RXID interface types

Currently dp83867 driver returns error if phy interface type
PHY_INTERFACE_MODE_RGMII_RXID is used to set the rx only internal
delay. Similarly issue happens for PHY_INTERFACE_MODE_RGMII_TXID.
Fix this by checking also the interface type if a particular delay
value is missing in the phy dt bindings. Also update the DT document
accordingly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 34c55cf2fc75f8bf6ba87df321038c064cf2d426)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: Ideca1aae2512f0ee2944bc751e47436d8d1746b6

UPSTREAM: net: phy: dp83867: Add documentation for optional impedance control

Add documention of ti,min-output-impedance and ti,max-output-impedance
which can be used to correct MAC impedance mismatch using phy extended
registers.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit d6081de7e011327af089475bb60593423963526a)
Change-Id: I5e1f90caff7fee13369302a84d1dac370cb75f5e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

net: phy: dp83867: Add binding for the CLK_OUT pin muxing option

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Change-Id: I416afa8ef29d9a684068fa880f99ca7b720cfd14
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: Recover from "port mirroring" N/A MODE4

The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ac6e058b75be71208e98a5808453aae9a17be480)
Change-Id: I1b17b6c88e76230fde3fd1c93c3bb09ee0c2790d
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: Add lane swapping support in the DP83867 TI's PHY driver

This patch adds support for enabling or disabling the lane swapping (called
"port mirroring" in PHY's CFG4 register) feature of the DP83867 TI's PHY
device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit fc6d39c39581f3c12c95f166ce95ef8beb2047e8)
Change-Id: Iea19a3e02a5072e5b3ab2b4ee33befd5805100e2
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: fix irq generation

For proper IRQ generation by DP83867 phy the INT/PWDN pin has to be
programmed as an interrupt output instead of a Powerdown input in
Configuration Register 3 (CFG3), Address 0x001E, bit 7 INT_OE = 1. The
current driver doesn't do this and as result IRQs will not be generated by
DP83867 phy even if they are properly configured in DT.

Hence, fix IRQ generation by properly configuring CFG3.INT_OE bit and
ensure that Link Status Change (LINK_STATUS_CHNG_INT) and Auto-Negotiation
Complete (AUTONEG_COMP_INT) interrupt are enabled. After this the DP83867
driver will work properly in interrupt enabled mode.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 5ca7d1ca77dc23934504b95a96d2660d345f83c2)
Change-Id: Ic4fd8e84a2e41f217850230699e00f603ea3f086
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: add support for MAC impedance configuration

Add support for programmable MAC impedance configuration

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit ed838fe937dbcdcf7c0444a5b62edfec6ecd753c)
Change-Id: I189307e95ccb4f71a245ec69df6f4ab0b32130ec
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: net: phy: dp83867: Fix initialization of PHYCR register

When initializing the PHY control register, the FIFO depth bits are
written without reading the previous register value, i.e. all other
bits are overwritten with zero. This disables automatic MDI-X
configuration, which is enabled by default. Fix initialization by doing
a read/modify/write operation.

Signed-off-by: Stefan Hauser <stefan@shauser.net>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit b291c418172f2cfbe009d81cd9a92f7a2de7c579)
Change-Id: If14021286ff6e8b770f6cfe0f4026e29414e75d8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: phy: phy_{read|write}_mmd_indirect: get addr from phydev

The address of the device can be determined from the phydev structure,
rather than passing it as a parameter.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 053e7e169229adebbc27fc176c5369398e9f5eba)
Change-Id: Ib0f855bb2f6ad38e37c030343d6ccb1cc8848178
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: PHY: DP83867: Remove looking in parent device for OF properties

Device tree properties for a phy device are expected to be in the phy
node. The current code for the DP83867 also tries to look in the
parent node. The devices binding documentation does not mention this,
no current device tree file makes use of this, and it is not behaviour
we want. So remove looking in the parent device.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 7bf9ae016efc0cf08263fbee5ac708c23b90792e)
Change-Id: Ia0b9f5fbe15b3c042880b8c8712c1b72f994029e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

UPSTREAM: leds: pca9532: Add device tree support

This patch adds basic device tree support for the pca9532 LEDs.

Signed-off-by: Phil Reid <preid@electromag.com.au>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
(cherry picked from commit fa4191a609f219262a18dd8b02ab7dc30896b707)
Change-Id: I4daef4193eef8c4cad883224048fa0b9ef03558f
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

ARM: dts: rockchip: add eDP panel support for Firefly

This patch adds the supporting to the eDP panel sold by
the T-CHIP for the Firefly RK3288. I assign the VOP lite
for the eDP panel and VOP big to HDMI, as the HDMI supports
4K resolution. With a different VOP device, eDP panel
and HDMI could display a different contents.

The InvenSense MPU6050 sensor at the botton of the panel
is also enabled.

The Firefly RK3288 Reload use a different GPIO pin to enable
the power of the eDP panel.

Change-Id: Id78249f001d171ede79fe835d24c40a75ff8a0df
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>

UPSTREAM: net: stmmac: dwmac-rk: Add handling for RGMII_ID/RXID/TXID

ATM dwmac-rk will always set and enable it's internal delay lines.
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.

Tested only with a RK3288 based board.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit eaf70ad14cbbb99d46b78b1307628a16a3f6075d)
Change-Id: Id0152a9f048cbc810b62c252d4105594ed1895df
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

FROMLIST: usb: dwc2: resume root hub to handle disconnect of device

When handle disconnect of the hcd during bus_suspend, hcd
needs to resume its root hub, otherwise the root hub will
not disconnect the existing devices under its port.

This issue always happens when connecting with usb devices
which support auto-suspend function (e.g. usb hub).

(am from https://patchwork.kernel.org/patch/9751469/)
Change-Id: I663fdea73f36e89130d9a250612363968cbff941
Signed-off-by: William Wu <william.wu@rock-chips.com>

usb: dwc_otg_310: fix reboot test fail in otg host mode

When do reboot test with otg cable plugging in, it may
casue two issues: 1. system hung when access grstctl reg
in dwc_otg_core_reset(); 2. kernel panic when remove the
host channel from the free list in assign_and_init_hc().

This patch adds 1.5~2ms delay afer resume USB2 PHY, the
time for utmi_clk provided from USB2 PHY to stabilize,
and then we can access the usb core registers safely, it
can avoid system hung.

Also, we avoid to call otg20_hcd_connect_detect() if dwc2
is host mode except force host mode during probe, because
we will do the same work in check_id_work() later. This can
fix the issue that init usb core and host twice when boot
with otg cable and usb device, which may cause kernel panic
because of hc list is NULL.

Change-Id: I35aa36762c64b14b580b493d213610379676ab56
Signed-off-by: William Wu <william.wu@rock-chips.com>

i2c: rk3x: Make sure the i2c transfer to be finished before system reboot

If the system rebooted, there might be i2c transfer at the
same time, it will make something unpredictable, because
the i2c host was reseted, but the slave device wasn't, such
as rk808 pmic, so make sure the i2c transfer to be finished
before system shutdown at the reset mode.

Change-Id: I3c09f3acbe86595c295edc191aa38351adb7d5dc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

ARM: rockchip: pm: fix compile warning

When build with ARM_LPAE enabled:
arch/arm/mach-rockchip/pm.c: In function 'rk3288_init_pmu_sram':
arch/arm/mach-rockchip/pm.c:85:23: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]

Change-Id: I526f13439c3c7edde77a27419d488a8f79081661
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

video/rockchip: fix rga driver compile when LPAE

Change-Id: Ifc50e0ae52ece8c93ab8fab4ddabc01916ace526
Signed-off-by: Zikim,Wei <wzq@rock-chips.com>
(cherry picked from commit c1f2cf28941e5a31e00b21025fe48260bb235b9a)

mmc: host: rk_sdmmc_ops: fix area access error

Change-Id: Ibc0655d630e808d6daccbb4c0f76ffc2afa930a2
Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

mfd: fusb302: move notify to PD startup state

The PD policy would take 5-7s to enter PD disabled state (send
50 times caps, the more bytes of caps cmd, the more time it
takes), So we ough to pick usb notify to PD startup state for
better user experience.

Change-Id: I3b2dc1c5df31296520685ba57e892a30ef3c28aa
Signed-off-by: zain wang <wzz@rock-chips.com>

mfd: fusb302: fix some variable following PD specification

In the spec:
The tTypeCSendSourceCap is defined from 100ms to 200ms.
The nCapsCount is defined 50.

Change-Id: I09bcdb7a83c353ab099d51228cf8ca13e562d839
Signed-off-by: zain wang <wzz@rock-chips.com>

mfd: fusb302: Add is_pd_support to struct fusb30x_chip

As the PD spec, we ough to tell policy engine if the cable
support PD, some state would run depend on this value.

Change-Id: Ied725ecb53f71a5e367b1ca91acd7f23372c54a1
Signed-off-by: zain wang <wzz@rock-chips.com>

drivers: vendor_storage: add retry when emmc initialize failed

Change-Id: I28202c5e3a4eb9ab58a430f40ff5e969fd110f54
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

arm: dts: rk3288-android: enable fiq debugger mode

Change-Id: I536439c95488eba7ff3f52e8df87d7e21eb76989
Signed-off-by: chenjh <chenjh@rock-chips.com>

ARM: rockchip_defconfig: enable CONFIG_FIQ_DEBUGGER_TRUST_ZONE

Signed-off-by: chenjh <chenjh@rock-chips.com>
Change-Id: I0235b755f1e3481aa9fa326f87261c7bd39ce039

USB: dwc_otg_310: pcd: don't set cnak when setup stage

Refer dwc2 databook and programming, the controller automatic
receive SETUP packet to the receive FIFO and respond to Host
ACK whether ep enabled or not. The core internally set the IN
NAK and OUT NAK bits when SETUP packet was received in order
to software process SETUP packet and transition to the next
stage.

If software has not enabled ep before the Host send the SETUP
packet, set enable ep and cnak at the same time the Host send
DATA OUT packet. Then dwc2 controller write the setup data to
the memory and disable ep, respond ACK to the Host DATA OUT
packet. The Host transition to the status stage, but we lost
the DATA OUT packet. So don't set cnak when setup stage, the
dwc2 controller respond NAK to the Host DATA OUT packet, the
Host resend ping packet and DATA OUT packet.

TEST=set gadget work as usb audio and connect to ubuntu(rk3036)

Change-Id: Id791c44baf3d363a975ceaeb7d1c879c9703ce1d
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>

ARM: dts: rockchip: add memory node for rk3229-echo-v10

when using upstream u-boot load kernel, reserves memory from early
allocator will fail if memory node is not specified.

===============================
Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0xf00
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacctdd
...
[    0.000000] earlycon: Early serial console at MMIO32 0x11030000 (options '')
[    0.000000] bootconsole [uart0] enabled
[    0.000000] cma: Failed to reserve 16 MiB
[    0.000000] Memory policy: Data cache writealloc

This patch fix it.

Change-Id: I6a3c6b1e210bbc9a5240503ab7bf5ddab89910ba
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

UPSTREAM: ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards

This patch fixes the following DTC warnings:

"Node /memory has a reg or ranges property, but no unit name"

Change-Id: I140cef24b80e4ff0b9fbe6f0e07221fba1da72f0
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 09fbc4a08e8c5b08540dd6758c6951f52b4b4e5f)

net: usb: modify rx_urb_size size for dm9601

fix error:
[  103.825058] DWC_OTG Transfer buffer length less than actual buffer lengthactual_length 1536 , buffer_length 1522 urb->complete rx_complete+0x0/0x1cc
[  103.839742] skbuff: skb_over_panic: text:ffffff80086e1f74 len:1536 put:1536 head:ffffffc06118da80 data:ffffffc06118dac2 tail:0x642 end:0x640 dev:eth0
[  103.839960] ------------[ cut here ]------------
[  103.839989] kernel BUG at net/core/skbuff.c:104!
[  103.840027] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[  104.008320] read channel() error: -110
[  104.218321] read channel() error: -110
[  104.428304] read channel() error: -110
[  104.638314] read channel() error: -110
[  104.848296] read channel() error: -110
[  105.058314] read channel() error: -110
[  105.268303] read channel() error: -110
[  105.280141] Modules linked in: pvrsrvkm(O)
[  105.284297] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W  O    4.4.66 #26
[  105.291524] Hardware name: Rockchip rk3368 p9 board (DT)
[  105.296850] task: ffffff8009165090 ti: ffffff8009150000 task.ti: ffffff8009150000
[  105.304352] PC is at skb_panic+0x4c/0x50
[  105.308290] LR is at skb_panic+0x4c/0x50
[  105.312227] pc : [<ffffff80089436f8>] lr : [<ffffff80089436f8>] pstate: 604001c5
[  105.319624] sp : ffffffc07db5b890
[  105.322948] x29: ffffffc07db5b8a0 x28: 0000000000000002
[  105.328296] x27: ffffff80095805ec x26: ffffff80095805e8
[  105.333643] x25: 0000000000000002 x24: 0000000000000002
[  105.338988] x23: ffffff80095805e0 x22: ffffffc06114fb00
[  105.344335] x21: 0000000000000000 x20: ffffffc047837b40
[  105.349683] x19: ffffffc0793ac800 x18: 0000000000000000
[  105.355029] x17: 00000078da08d124 x16: ffffff80081f1438
[  105.360376] x15: 000000000000000c x14: 636666666666663a
[  105.365723] x13: 6461656820363335 x12: 313a747570203633
[  105.371071] x11: 35313a6e656c2034 x10: 3766316536383030
[  105.376417] x9 : 386666666666663a x8 : 303a646e65203234
[  105.381764] x7 : 000000000000000a x6 : 000000000000000d
[  105.387110] x5 : 0000000000000001 x4 : 0000000000000001
[  105.392455] x3 : 0000000000000007 x2 : cb88537fdc8ba642
[  105.397802] x1 : cb88537fdc8ba642 x0 : 0000000000000089

Change-Id: Ie11f20d62bec7d0d35b82d0bb5535d3c8d9213b9
Signed-off-by: zzc <zzc@rock-chips.com>

arm: dts: rk322x-android: enable rockchip-suspend

Change-Id: I49ecf3e733ec376f86dc4ab7f27f3c1e0af964eb
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

arm: dts: rk322x: add rockchip-suspend node

Change-Id: I1bdc66e4e8db55cdc02709bf0eb901ea037c5a60
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

soc: rockchip: support rk322x pm config

Change-Id: I29c5685f09a846b62196ab8614ebe168bfed75ef
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

clk: rockchip: rk3328: add flag CLK_IGNORE_UNUSED for hclk_vop_niu

Change-Id: I770a83ad357f18d3258755b6c1d43ef82248951e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

ARM64: dts: rockchip: rk3399-opp: fix up the gpu_opp_table

Change-Id: I2e13b74ce3ff8509753605b9b0a02fb1c8d0f765
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm64: dts: rk3399: sapphire: set syr83x vsel gpio type input

Change-Id: I5c809885038e81570d993ebbc94ae757ba4b9acd
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

driver: sensor-dev: use copy_to_user&&copy_from_user to do the user point

Change-Id: Ibbff2eecc71643c95ae91d0cd8a8469fd43a3cea
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

power: rk818-charger: move irq init to the last step

init irq later than workqueue_struct and delayed_work to
avoid NULL ponint

Change-Id: I715296a715cb07149a6dce236a3b8ccafe00622e
Signed-off-by: chenjh <chenjh@rock-chips.com>

drm/rockchip: vop: support vop dump when iommu page fault

Change-Id: I164fc7e8cb7392143959d53709bcdf61713fb3d8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rk3368: add dfi and dmc device nodes

Add dfi and dmc nodes in the device tree for the ARM64 rk3368 SoC.
To support ddr frequency scaling function, we need enable dmc and
dfi nodes.

Change-Id: I155b838a8773ff1842058bebb1ed2747ca8e2e0b
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

power: rk818-charger: add TS2 voltage detect when update input current

rk818's input charge voltage limit function doesn't works well. If software
set input current over than charger's max support value, rk818 may cause
charger over current protect which means disconnecting.
To solve this problem, we need to detect vbus voltage by TS2 pin, if vbus
is upper than 4.4v, we can safely adjust input current step by step from
low to high until meeting the target input current value.

Change-Id: I01d63974f251ad8ef0037158b66f4b85d3928baf
Signed-off-by: chenjh <chenjh@rock-chips.com>

ASoc: hdmi_codec: fix startup error when multicodecs are used

due to playback and capture will call startup at the same time
when voip call, but hdmi_codec driver only support playback

[   51.134149] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[   51.134179] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[   51.134197] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22
[   51.143250] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[   51.143277] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[   51.143294] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22
[   51.157546] hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_startup()
[   51.157584] hdmi-audio-codec hdmi-audio-codec.6.auto: Only one simultaneous stream supported!
[   51.157603] hdmi-audio-codec hdmi-audio-codec.6.auto: ASoC: can't open codec i2s-hifi: -22

Change-Id: I970695dbe19f070579aacd044e6a01c44e687a2e
Signed-off-by: zhangjun <zhangjun@rock-chips.com>

arm64: dts: rk3368: add wakeup-config in rockchip-suspend

Change-Id: Ibf4ba154d59e99332e68ca5451b0045e15fa850d
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

net: wireless: rockchip_wlan: enable GET_CUSTOM_MAC_ENABLE

Change-Id: I544df96a365ab62b12388e5df3c2fcfa23204e32
Signed-off-by: zzc <zzc@rock-chips.com>

arm64: rockchip_defconfig: fix softap error

fix error:
05-16 06:42:05.688   347   596 V NatController: runCmd(/system/bin/ip6tables -w -t raw -A natctrl_raw_PREROUTING -i wlan0 -m rpfilter --invert ! -s fe80::/64 -j DROP) res=1
05-16 06:42:05.726   347   596 E NatController: Error setting forward rules
05-16 06:42:05.791   602   622 E TetherInterfaceSM: Exception enabling Nat: java.lang.IllegalStateException: command '53 nat enable wlan0 eth0 1 192.168.43.0/24' failed with '400 53 Nat op
eration failed (No such device)'
05-16 06:42:05.794   347   841 D TetherController: Sending update msg to dnsmasq [update_ifaces|wlan0]
05-16 06:42:05.796   347   596 D TetherController: untetherInterface(wlan0)

Change-Id: Iae2ec50bef0915aecc1b2befb014a87731e61643
Signed-off-by: zzc <zzc@rock-chips.com>