"." isn't enough to get a private label on linux, use ".L".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26327 91177308-0d34-0410-b5e6-96231b3b80d8

add a small and simple case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26326 91177308-0d34-0410-b5e6-96231b3b80d8

A couple of new entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26325 91177308-0d34-0410-b5e6-96231b3b80d8

PIC related bug fixes.
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26324 91177308-0d34-0410-b5e6-96231b3b80d8

X86 codegen tweak to use lea in another case:

Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26323 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test case for 'lea'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26322 91177308-0d34-0410-b5e6-96231b3b80d8

Missing .globl for weak / link-once .text symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26321 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Regression/Transforms/LoopUnswitch/2006-02-22-UnswitchCrash.ll, which
caused SPASS to fail building last night.

We can't trivially unswitch a loop if the exit block has phi nodes in it,
because we don't know which predecessor to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26320 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase distilled from SPASS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26319 91177308-0d34-0410-b5e6-96231b3b80d8

This fixes a couple of problems with expansion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26318 91177308-0d34-0410-b5e6-96231b3b80d8

Don't return registers from register classes that aren't legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26317 91177308-0d34-0410-b5e6-96231b3b80d8

Change a whole bunch of code to be built around RegsForValue instead of
a single register number.  This fully implements promotion for inline asms,
expand is close but not quite right yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8

- Added option -relocation-model to set relocation model. Valid values include static, pic,
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8

Coordinate activities with llvm-gcc4 and dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26314 91177308-0d34-0410-b5e6-96231b3b80d8

Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.

Patch by Martin Partel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26313 91177308-0d34-0410-b5e6-96231b3b80d8

Turn on loop unswitching tonight

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26312 91177308-0d34-0410-b5e6-96231b3b80d8

Add some comments, simplify some code, and fix a bug that caused rewriting
to rewrite with the wrong value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26311 91177308-0d34-0410-b5e6-96231b3b80d8

Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26310 91177308-0d34-0410-b5e6-96231b3b80d8

reorder some libraries

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26309 91177308-0d34-0410-b5e6-96231b3b80d8

split register class handling from explicit physreg handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8

expose the set of values types holdable in a regclass to clients

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26307 91177308-0d34-0410-b5e6-96231b3b80d8

Adjust to changes in getRegForInlineAsmConstraint prototype

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8

Updates to match change of getRegForInlineAsmConstraint prototype

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8

Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
select different sets of registers depending on the type requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26304 91177308-0d34-0410-b5e6-96231b3b80d8

One more round of reorg so sabre doesn't freak out. :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26303 91177308-0d34-0410-b5e6-96231b3b80d8

A big more cleaning up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8

Moving things to their proper places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26301 91177308-0d34-0410-b5e6-96231b3b80d8

Split instruction info into multiple files, one for each of x87, MMX, and SSE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26300 91177308-0d34-0410-b5e6-96231b3b80d8

missed optzn

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26299 91177308-0d34-0410-b5e6-96231b3b80d8

The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
instructions are expensive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26298 91177308-0d34-0410-b5e6-96231b3b80d8

Added separate alias instructions for SSE logical ops that operate on non-packed types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26297 91177308-0d34-0410-b5e6-96231b3b80d8

Added MMX and XMM packed integer move instructions, movd and movq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26296 91177308-0d34-0410-b5e6-96231b3b80d8

Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8

Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8

Some updates

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26292 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem Nate and Duraid reported where simplifying nodes can cause
them to get ressurected, in which case, deleting the undead nodes is
unfriendly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26291 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a problem on itanium with memset.  The value to set has been promoted to
i64 before this code, so zero_ext doesn't work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26290 91177308-0d34-0410-b5e6-96231b3b80d8

improved support for branch folding, still not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26289 91177308-0d34-0410-b5e6-96231b3b80d8

If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
advantage of fisttpll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26288 91177308-0d34-0410-b5e6-96231b3b80d8

Fix bugs identified by VC++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26287 91177308-0d34-0410-b5e6-96231b3b80d8

Add a fold for add that exchanges it with a constant shift if possible, so
that the shift may be more easily folded into other operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26286 91177308-0d34-0410-b5e6-96231b3b80d8

Implement deletion of dead blocks, currently disabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26285 91177308-0d34-0410-b5e6-96231b3b80d8

Add checks to make sure we don't create bogus extend nodes, and fix a bug
where we were doing exactly that which was causing failures on x86 and
alpha.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26284 91177308-0d34-0410-b5e6-96231b3b80d8

Added fisttp for fp to int conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26283 91177308-0d34-0410-b5e6-96231b3b80d8

Bump up pattern cost if the resulting instruction is marked
usesCustomDAGSchedInserter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26282 91177308-0d34-0410-b5e6-96231b3b80d8

Disable PIC for JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26281 91177308-0d34-0410-b5e6-96231b3b80d8

a previous patch completely disabled trivial unswitching, this fixees it.
Thanks to nate for pointing this out :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26280 91177308-0d34-0410-b5e6-96231b3b80d8

initial trivial support for folding branches that have now-constant destinations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26279 91177308-0d34-0410-b5e6-96231b3b80d8

Jit does not support PIC yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26278 91177308-0d34-0410-b5e6-96231b3b80d8

When unswitching a loop, make sure to update loop info with exit blocks in
the right loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26277 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Transforms/SimplifyCFG/2006-02-17-InfiniteUnroll.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26275 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase that crashes simplifycfg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26274 91177308-0d34-0410-b5e6-96231b3b80d8

x86 / Darwin PIC support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8

Moved PICEnabled to include/llvm/Target/TargetOptions.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26272 91177308-0d34-0410-b5e6-96231b3b80d8

Move PICEnabled declaration here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26271 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a tricky issue in the SimplifyDemandedBits code where CombineTo wasn't
exactly the API we wanted to call into.  This fixes the crash on crafty last
night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26269 91177308-0d34-0410-b5e6-96231b3b80d8

add a new method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26268 91177308-0d34-0410-b5e6-96231b3b80d8

A few final (for now) tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26267 91177308-0d34-0410-b5e6-96231b3b80d8

Yet another test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26266 91177308-0d34-0410-b5e6-96231b3b80d8

New tests!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26265 91177308-0d34-0410-b5e6-96231b3b80d8

Added documentation for vset and vselect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26264 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up DemandedBitsAreZero interface
Make more use of the new mask helpers in valuetypes.h
Combine (sra (srl x, c1), c1) -> sext_inreg if legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26263 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a nit sabre noticed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26262 91177308-0d34-0410-b5e6-96231b3b80d8

Don't expand sdiv by power of two before legalize, since it will likely
generate illegal nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26261 91177308-0d34-0410-b5e6-96231b3b80d8

unbreak the build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26260 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak x86 be

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26259 91177308-0d34-0410-b5e6-96231b3b80d8

Fix loops where the header has an exit, fixing a loop-unswitch crash on crafty

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26258 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a comment sabre noticed :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26257 91177308-0d34-0410-b5e6-96231b3b80d8

A couple new regression tests to make sure we always pattern match the new
opcodes on ppc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26256 91177308-0d34-0410-b5e6-96231b3b80d8

kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another miscompilation exposed by lencode, where we lowered i64->f32
conversions to __floatdidf instead of __floatdisf on targets that support
f32 but not i64 (e.g. sparc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26254 91177308-0d34-0410-b5e6-96231b3b80d8

add note about div by power of 2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26253 91177308-0d34-0410-b5e6-96231b3b80d8

Fix bug noticed by VC++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26252 91177308-0d34-0410-b5e6-96231b3b80d8

Inform Visual Studio of deleted file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26251 91177308-0d34-0410-b5e6-96231b3b80d8

Whoops, didn't mean to check this in yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26250 91177308-0d34-0410-b5e6-96231b3b80d8

Add a missing and useful pat frag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26249 91177308-0d34-0410-b5e6-96231b3b80d8

start of some new simplification code, not thoroughly tested, use at your own
risk :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26248 91177308-0d34-0410-b5e6-96231b3b80d8

Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
issue. Need to do more experiments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26247 91177308-0d34-0410-b5e6-96231b3b80d8

Kill the x86 pattern isel.  boom.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26246 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the entry about using movapd for SSE reg-reg moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26245 91177308-0d34-0410-b5e6-96231b3b80d8

pxor (for FLD0SS) encoding was missing the OpSize prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26244 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the skeleton target, it doesn't produce useful code and there are
other small targets that do that can be learned from.  They also have
the added advantage of being tested :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26243 91177308-0d34-0410-b5e6-96231b3b80d8

Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
turns out not to point to a constant string but it forgot change the offset
back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26242 91177308-0d34-0410-b5e6-96231b3b80d8

1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26241 91177308-0d34-0410-b5e6-96231b3b80d8

Use movaps / movapd to spill / restore V4F4 / V2F8 registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26240 91177308-0d34-0410-b5e6-96231b3b80d8

remove skeleton target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26239 91177308-0d34-0410-b5e6-96231b3b80d8

Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8

don't build the skeleton target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26237 91177308-0d34-0410-b5e6-96231b3b80d8

remove support for the skeleton target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26236 91177308-0d34-0410-b5e6-96231b3b80d8

Change SplitBlock to increment a BasicBlock::iterator, not an Instruction*.  Apparently they do different things :)

This fixes a testcase that nate reduced from spass.

Also included are a couple minor code changes that don't affect the generated
code at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26235 91177308-0d34-0410-b5e6-96231b3b80d8

MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26234 91177308-0d34-0410-b5e6-96231b3b80d8

distinguish between objects and register names, now we can have stuff
with names like "f84", "in6" etc etc.

this should fix one or two tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26232 91177308-0d34-0410-b5e6-96231b3b80d8

If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8

Lowering of sdiv X, pow2 was broken, this fixes it.  This patch is written
by Nate, I'm just committing it for him.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26230 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a minor makefile bug with lex/yacc handling that nate noticed.  We don't
want to copy the files when the .cpp file changes, we want to copy them
to the .cvs versions when the .l/.y file change (like the comments even say).
This avoids having bogus changes show up in diffs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26229 91177308-0d34-0410-b5e6-96231b3b80d8

Fix VC++ warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26228 91177308-0d34-0410-b5e6-96231b3b80d8

Visual Studio enters the future of bisoning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26227 91177308-0d34-0410-b5e6-96231b3b80d8

Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26226 91177308-0d34-0410-b5e6-96231b3b80d8

fix a bug where we unswitched the wrong way

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26225 91177308-0d34-0410-b5e6-96231b3b80d8

A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8