Rename ConvertType to ConvertConstant to avoid a name conflict on llvm-gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78596 91177308-0d34-0410-b5e6-96231b3b80d8

SimpleValueType-ify a few more methods on TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78595 91177308-0d34-0410-b5e6-96231b3b80d8

Handle the constantfp created during post-legalization dag combiner phase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78594 91177308-0d34-0410-b5e6-96231b3b80d8

Continue the SimpleValueType-ification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78593 91177308-0d34-0410-b5e6-96231b3b80d8

Fix ocaml "make check" tests, that wasn't finding the proper c++ compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78592 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment in llvm.mli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78591 91177308-0d34-0410-b5e6-96231b3b80d8

Convert comments to C90-style so llvm-c can import DataTypes.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78590 91177308-0d34-0410-b5e6-96231b3b80d8

Fix docstring for ocaml binding's const_float.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78589 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Remove some code which has been obsoleted by move to
explicit parser match classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78588 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Fix thinko, Mem isn't a subclass of Imm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78587 91177308-0d34-0410-b5e6-96231b3b80d8

We are not using FoldingSet for metadata uniquing anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78585 91177308-0d34-0410-b5e6-96231b3b80d8

Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Change assembler parser match classes to their own record
structure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78581 91177308-0d34-0410-b5e6-96231b3b80d8

g++ 4.0 doesn't have std::vector::data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78579 91177308-0d34-0410-b5e6-96231b3b80d8

Change the MDNode uniquing to a ValueMap, at Devang's request.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78577 91177308-0d34-0410-b5e6-96231b3b80d8

split MachO section handling stuff out to its out .h/.cpp file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78576 91177308-0d34-0410-b5e6-96231b3b80d8

add a fixme

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78575 91177308-0d34-0410-b5e6-96231b3b80d8

arm only needs to emit one .align directive for hidden nlp's, not one
per pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78574 91177308-0d34-0410-b5e6-96231b3b80d8

make sure that arm nonlazypointers are aligned properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78573 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a weird ppc64-specific link error during an llvm-gcc build:
ld: bad offset (0x00000091) for lo14 instruction pic-base fix-up in ___popcountdi2 from libgcc/./_popcountsi2_s.o

The problem is that the non lazy symbol pointers need to be 8 byte aligned
on ppc64 and .section doesn't have an implicit alignment like ".non_lazy_symbol_pointer"
does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78572 91177308-0d34-0410-b5e6-96231b3b80d8

fix some warnings for the MSVC build, by Yonggang Luo!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78571 91177308-0d34-0410-b5e6-96231b3b80d8

Make this comment more closely reflect the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78569 91177308-0d34-0410-b5e6-96231b3b80d8

Add nounwind keywords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78568 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for printing loop structure information in asm comments.
This definitely slows down asm output so put it under an -asm-exuberant
flag.

This information is useful when doing static analysis of performance
issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78567 91177308-0d34-0410-b5e6-96231b3b80d8

Clarify limitations of a ModulePass requiring a FunctionPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78566 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Check for matches with super classes when matching
instruction operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78565 91177308-0d34-0410-b5e6-96231b3b80d8

Checkpoint scheduling itinerary changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8

Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8

Watch out for empty BB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78562 91177308-0d34-0410-b5e6-96231b3b80d8

rev, rev16, and revsh do not set CPSR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8

Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8

CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for folding loads / stores into 16-bit moves used by Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78558 91177308-0d34-0410-b5e6-96231b3b80d8

80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78557 91177308-0d34-0410-b5e6-96231b3b80d8

Use tMOVgpr2gpr instead of t2MOVr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for a user supplied pointer argument to llvm_install_error_handler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78553 91177308-0d34-0410-b5e6-96231b3b80d8

Move ConstantExpr handling to ResolveConstantExpr method and also
add support for PtrToInt, Add, Mul.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78552 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to reduce most of 32-bit Thumb2 arithmetic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8

Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8

Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string.  This means that it keeps track of the
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and
"attribute(section)", so we should now start getting errors about invalid
section attributes from the compiler instead of the assembler on darwin.

Still todo:
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78547 91177308-0d34-0410-b5e6-96231b3b80d8

add a simple back() method to StringRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78544 91177308-0d34-0410-b5e6-96231b3b80d8

Use abs64 instead abs; some platforms don't have a 64-bit abs overload. Noticed by Yonggang Luo!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78543 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to convert 32-bit instructions to 16-bit non-two-address ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8

always end a section with \n on elf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78534 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Fix thinko in ClassInfo::operator<.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78533 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Add hack to ignore Int_* and *_Int instructions for now, to
make it easier to see interesting ambiguities.
 - Also, check that user doesn't try to redefine the super class. This is a wart
   in the current design, in that assembler match classes aren't explicitly
   declared somewhere (so there isn't a unique place to declare the super
   class). This should probably be fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78532 91177308-0d34-0410-b5e6-96231b3b80d8

Disable this test for now, we don't check for super classes when matching yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78531 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Implement user defined super classes.
 - We can now discriminate SUB32ri8 from SUB32ri, for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78530 91177308-0d34-0410-b5e6-96231b3b80d8

Add tests for Neon VZIP and VUZP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78529 91177308-0d34-0410-b5e6-96231b3b80d8

Add a test for Neon VTRN instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78528 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Separate instruction ordering for ambiguity detection.
 - We want the ordering operation to be simple, since we run it on every
   match. The old ordering is also not a strict weak ordering when there are
   ambiguities, which makes MSVC unhappy.

 - While we are at it, detect all ambiguities instead of just the adjacent
   ones. There are actually 655, for X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78526 91177308-0d34-0410-b5e6-96231b3b80d8

Change Neon table lookup (VTBL) and table extension (VTBX) intrinsics to
take the table vectors as separate arguments, instead of the previous
approach where they were combined into one big vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78525 91177308-0d34-0410-b5e6-96231b3b80d8

Extend comment on ParserMatchClass .td field, and add some missing
classes for X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78524 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Define match classes in the .td file.
 -2 FIXMEs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78523 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmParser: Sketch infrastructure for ordering instructions & detecting
ambiguities.
 - Currently there are 483 ambiguities to resolve. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78522 91177308-0d34-0410-b5e6-96231b3b80d8

STLExtras: Add less_ptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78521 91177308-0d34-0410-b5e6-96231b3b80d8

fix edito

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78520 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Tweak string matcher (missed a newline).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78518 91177308-0d34-0410-b5e6-96231b3b80d8

sink the 'name' and 'isdirective' state out of MCSection into its derived classes.
This totally optimizes PIC16 sections by not having an 'isdirective' bit anymore!! ;-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78517 91177308-0d34-0410-b5e6-96231b3b80d8

Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Tweak string matcher.
 - Track whether we need to insert an explicit 'break'.

 - Invert conditional when matching a single prefix to reduce
   nesting/bracing/breaking.

 - wc -l of X86GenAsmMatcher.inc decreased by 10%. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78513 91177308-0d34-0410-b5e6-96231b3b80d8

remove nondeterminstic test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78512 91177308-0d34-0410-b5e6-96231b3b80d8

add a note about dead zero extends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78511 91177308-0d34-0410-b5e6-96231b3b80d8

1. Make MCSection an abstract class.
2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and
   TLOFELF::AtIsCommentChar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78510 91177308-0d34-0410-b5e6-96231b3b80d8

switch this to create coff sections for now, it doesn't really matter for
llvm-mc's purpose yet and we'll want to switch to creating semantic sections
at some point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78509 91177308-0d34-0410-b5e6-96231b3b80d8

Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for READCYCLECOUNTER in Blackfin back-end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78506 91177308-0d34-0410-b5e6-96231b3b80d8

add new PIC16Section class, this time hopefully not breaking the build :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78505 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Switch token matching to use the new string matcher.

Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78504 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r78501, it doesn't build.

 --- Reverse-merging r78501 into '.':
U    lib/Target/PIC16/PIC16TargetObjectFile.cpp
D    lib/Target/PIC16/PIC16Section.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78503 91177308-0d34-0410-b5e6-96231b3b80d8

make PIC16 create its own custom MCSection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78501 91177308-0d34-0410-b5e6-96231b3b80d8

make target-specific TLOF impls (except PIC16) create target-specific
MCSection instances.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78500 91177308-0d34-0410-b5e6-96231b3b80d8

stub out PECOFF/MachO/ELF MCSection classes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78499 91177308-0d34-0410-b5e6-96231b3b80d8

eliminate TargetLoweringObjectFileSparc in favor of a TAI hook.
A TAI hook is appropriate in this case because this is just an
asm syntax issue, not a semantic difference. TLOF should model
the semantics of the section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78498 91177308-0d34-0410-b5e6-96231b3b80d8

Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().

Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78497 91177308-0d34-0410-b5e6-96231b3b80d8

give pic16 a target-specific section creation name too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78496 91177308-0d34-0410-b5e6-96231b3b80d8

now that getOrCreateSection is all object-file specific,
give the impls an object-file-specific name.  In the future
they can take different arguments etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78495 91177308-0d34-0410-b5e6-96231b3b80d8

sink getOrCreateSection down into all the object file implementations,
now that they create *all* the sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78494 91177308-0d34-0410-b5e6-96231b3b80d8

Fix some cut and paste-os.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78493 91177308-0d34-0410-b5e6-96231b3b80d8

add a little function to do arbitrary string pattern matching in a
much more efficient way than a sequence of if's.  Switch MatchRegisterName
to use it.  It would be nice if someone could factor this out to a shared
place in tblgen :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78492 91177308-0d34-0410-b5e6-96231b3b80d8

add another const

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78487 91177308-0d34-0410-b5e6-96231b3b80d8

remove a useless anon-ns, make table const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78486 91177308-0d34-0410-b5e6-96231b3b80d8

Some ProfileInfo cleanups.
 - Part of optimal static profiling patch sequence by Andreas Neustifter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78485 91177308-0d34-0410-b5e6-96231b3b80d8

Add a basic static ProfileInfo provider (ProfileEstimatorPass).
 - Part of optimal static profiling patch sequence by Andreas Neustifter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78484 91177308-0d34-0410-b5e6-96231b3b80d8

Define intrinsics for crc instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78482 91177308-0d34-0410-b5e6-96231b3b80d8

Use reloc_absolute_word_sext relocation for X86::MOV64(ri/mi)32 instructions,
since they are in 64 bit mode with i64immSExt32 imms. JIT is not affected since
it handles both word absolute relocations in the same way

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78479 91177308-0d34-0410-b5e6-96231b3b80d8

More ProfileInfo improvements.
 - Part of optimal static profiling patch sequence by Andreas Neustifter.

 - Store edge, block, and function information separately for each functions
   (instead of in one giant map).

 - Return frequencies as double instead of int, and use a sentinel value for
   missing information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78477 91177308-0d34-0410-b5e6-96231b3b80d8

ELF improvements:
Handle large integers, x86_fp80, ConstantAggregateZero, and two more ConstantExpr:
GetElementPtr and IntToPtr
Set SHF_MERGE bit for mergeable strings
Avoid zero initialized strings to be classified as a bss symbol
Don't allow common symbols to be classified as STB_WEAK
Add a constant to be used as a global value offset in data relocations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78476 91177308-0d34-0410-b5e6-96231b3b80d8

Update CMake

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78475 91177308-0d34-0410-b5e6-96231b3b80d8

Clean out per-function data after the machine code verifier is done with it.

Also don't dereference old pointers after they have been deleted causing
random crashes when enabling the machine code verifier.

Ahem...

I have not included a test case for the crash. It hapened when enabling the
verifier on CodeGen/X86/2009-08-06-branchfolder-crash.ll.

The crash depends on an MBB being allocated at the same address as a
previously deleted MBB. I don't think that can be reproduced reliably.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78472 91177308-0d34-0410-b5e6-96231b3b80d8

Add insert_elt / extract_elt patterns for v4f32 stuff.
Did anyone tests v4f32 ever?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78470 91177308-0d34-0410-b5e6-96231b3b80d8

Lane number should be printed w/o hash

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78469 91177308-0d34-0410-b5e6-96231b3b80d8

Use VLDM / VSTM to spill/reload 128-bit Neon registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78468 91177308-0d34-0410-b5e6-96231b3b80d8

Update the machine code verifier to keep up with the scavenger.

* Cleaner handling of <undef>.
* <def> takes precedence over <def,dead>.
* Implement the OK-to-redefine-a-register-that-was-
  live-in-but-has-not-been-used-before rule.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78467 91177308-0d34-0410-b5e6-96231b3b80d8

Remove RegisterScavenger::isSuperRegUsed(). This completely reverses the mistaken commit r77904.

Now there is no special treatment of instructions that redefine part of a
super-register. Instead, the super-register is marked with <imp-use,kill> and
<imp-def>. For instance, from LowerSubregs on ARM:

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1<undef>, %D1<kill>, 5
subreg: %D2<def> = FCPYD %D1<kill>, 14, %reg0, %Q1<imp-def>

subreg: CONVERTING: %Q1<def> = INSERT_SUBREG %Q1, %D0<kill>, 6
subreg: %D3<def> = FCPYD %D0<kill>, 14, %reg0, %Q1<imp-use,kill>, %Q1<imp-def>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78466 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify RegScavenger::forward a bit more.

Verify that early clobber registers and their aliases are not used.

All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.

The included test case is from PR4686. It has behaviour that was dependent on the order of operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78465 91177308-0d34-0410-b5e6-96231b3b80d8

move this fp select into a pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78464 91177308-0d34-0410-b5e6-96231b3b80d8

Always initialize AsmConds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78463 91177308-0d34-0410-b5e6-96231b3b80d8

MSVC doesn't like member variables with the same name as the class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78462 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-mc/AsmMatcher: Improve match code.
 - This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78461 91177308-0d34-0410-b5e6-96231b3b80d8