Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>

The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8

Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144777 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144776 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144774 91177308-0d34-0410-b5e6-96231b3b80d8

Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
looking at the size of the pointee. Fixes PR11390!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144773 91177308-0d34-0410-b5e6-96231b3b80d8

If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144772 91177308-0d34-0410-b5e6-96231b3b80d8

RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144771 91177308-0d34-0410-b5e6-96231b3b80d8

Process all uses first before defs to accurately capture register liveness. rdar://10449480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144770 91177308-0d34-0410-b5e6-96231b3b80d8

Fix testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144769 91177308-0d34-0410-b5e6-96231b3b80d8

CONCAT_VECTORS can have more than two operands.  PR11389.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144768 91177308-0d34-0410-b5e6-96231b3b80d8

Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144767 91177308-0d34-0410-b5e6-96231b3b80d8

Remove extra ,.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144759 91177308-0d34-0410-b5e6-96231b3b80d8

AddressSanitizer, first commit (compiler module only)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144758 91177308-0d34-0410-b5e6-96231b3b80d8

Object/Archive: Give Child a operator < for map.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144757 91177308-0d34-0410-b5e6-96231b3b80d8

Support/COFF: Add structs and enums from the standard for image files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144756 91177308-0d34-0410-b5e6-96231b3b80d8

llvm-objdump: Ignore non-objects in archives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144755 91177308-0d34-0410-b5e6-96231b3b80d8

test commit to verify that commit access works (added blank line)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144748 91177308-0d34-0410-b5e6-96231b3b80d8

Rename MVT::untyped to MVT::Untyped to match similar nomenclature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8

Fix SCEV overly optimistic back edge taken count for multi-exit loops.

Fixes PR11375: Different results for 'clang++ huh.cpp'...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144746 91177308-0d34-0410-b5e6-96231b3b80d8

Add FIXME comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8

Enable -widen-vmovs by default.

This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144734 91177308-0d34-0410-b5e6-96231b3b80d8

Stabilize the output of the dwarf accelerator tables. Fixes a comparison
failure during bootstrap with it turned on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144731 91177308-0d34-0410-b5e6-96231b3b80d8

GEPs with all zero indices are trivially coalesced by fast-isel.  For example,

%arrayidx135 = getelementptr inbounds [4 x [4 x [4 x [4 x i32]]]]* %M0, i32 0, i64 0
%arrayidx136 = getelementptr inbounds [4 x [4 x [4 x i32]]]* %arrayidx135, i32 0, i64 %idxprom134

Prior to this commit, the GEP instruction that defines %arrayidx136 thought that
%arrayidx135 was a trivial kill.  The GEP that defines %arrayidx135 doesn't
generate any code and thus %M0 gets folded into the second GEP.  Thus, we need
to look through GEPs with all zero indices.
rdar://10443319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144730 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing for register range syntax for VLD/VST register lists.

For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8

Merge ObjCPropertyDebugInfo.html  into SourceLevelDebugging.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144724 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing for data type suffices on NEON VMOV aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144722 91177308-0d34-0410-b5e6-96231b3b80d8

Fix MSVC warnings by adding a cast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144721 91177308-0d34-0410-b5e6-96231b3b80d8

AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8

jakob fixed X87 inline asm!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144719 91177308-0d34-0410-b5e6-96231b3b80d8

add ImmutableSet/Map dox, patch by Caitlin Sadowski!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144716 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/X86/dec-eflags-lower.ll: Relax expression for win32 x64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144714 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing two operand forms for shift instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8

add PTX backend info

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144711 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VFP assembly parsing for VADD and VSUB two-operand forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8

ARM accept an immediate offset in memory operands w/o the '#'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144709 91177308-0d34-0410-b5e6-96231b3b80d8

some notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144708 91177308-0d34-0410-b5e6-96231b3b80d8

Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8

ARM enclosing curly braces optional on one-register VLD/VST instruction lists.

'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144701 91177308-0d34-0410-b5e6-96231b3b80d8

Update section "MIPS Target Improvements" in the llvm 3.0 release notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144699 91177308-0d34-0410-b5e6-96231b3b80d8

ARM size suffix on VFP single-precision 'vmov' is optional.

rdar://10435114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8

Insert modified DBG_VALUE into LiveDbgValueMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144696 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144695 91177308-0d34-0410-b5e6-96231b3b80d8

ARM alternate size suffices for VTRN instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a misplaced paren bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144692 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.

Yet more of rdar://10435076.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing for two-operand form of 'mul' instruction.

rdar://10449856.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing for two-operand form of 'mul' instruction.

Ongoing rdar://10435114.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8

Testcase for r144684.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 two-operand 'mul' instruction wide encoding parsing.

rdar://10449724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144683 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 assembly parsing for mul.w in IT block fix.

When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8

StringRefize and simplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144675 91177308-0d34-0410-b5e6-96231b3b80d8

We currently use a callback to handle an IL pass deleting a BB that still
has a reference to it. Unfortunately, that doesn't work for codegen passes
since we don't get notified of MBB's being deleted (the original BB stays).

Use that fact to our advantage and after printing a function, check if
any of the IL BBs corresponds to a symbol that was not printed. This fixes
pr11202.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144674 91177308-0d34-0410-b5e6-96231b3b80d8

Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit
registers and instructions when ABI is N64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144666 91177308-0d34-0410-b5e6-96231b3b80d8

Set nomacro before emitting the sequence of instructions that set global pointer
register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144665 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify function PassByValArg64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144664 91177308-0d34-0410-b5e6-96231b3b80d8

Remove function printMipsSymbolRef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144663 91177308-0d34-0410-b5e6-96231b3b80d8

Remove Value::getNameStr. It has been deprecated for a while and provides no additional value over getName().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144657 91177308-0d34-0410-b5e6-96231b3b80d8

Missed some users of Value::getNameStr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144656 91177308-0d34-0410-b5e6-96231b3b80d8

Delete files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144655 91177308-0d34-0410-b5e6-96231b3b80d8

Remove MipsMCSymbolRefExpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144654 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144650 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144649 91177308-0d34-0410-b5e6-96231b3b80d8

Remove all remaining uses of Value::getNameStr().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8

Twinify GraphWriter a little bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144647 91177308-0d34-0410-b5e6-96231b3b80d8

Check all overlaps when looking for used registers.

A function using any RC alias is enough to enable the ExeDepsFix pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144636 91177308-0d34-0410-b5e6-96231b3b80d8

Make use of MachinePointerInfo::getFixedStack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144635 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some unnecessary includes of PseudoSourceValue.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144634 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144633 91177308-0d34-0410-b5e6-96231b3b80d8

Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some unnecessary includes of PseudoSourceValue.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r144611 and r144613.

These tests are actually correct, clang was miscompiling ExeDepsFix::processUses.

Evan fixed the miscompilation in r144628.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144630 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8

Set SeenStore to true to prevent loads from being moved; also eliminates a non-deterministic behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144628 91177308-0d34-0410-b5e6-96231b3b80d8

Rather than trying to use the loop block sequence *or* the function
block sequence when recovering from unanalyzable control flow
constructs, *always* use the function sequence. I'm not sure why I ever
went down the path of trying to use the loop sequence, it is
fundamentally not the correct sequence to use. We're trying to preserve
the incoming layout in the cases of unreasonable control flow, and that
is only encoded at the function level. We already have a filter to
select *exactly* the sub-set of blocks within the function that we're
trying to form into a chain.

The resulting code layout is also significantly better because of this.
In several places we were ending up with completely unreasonable control
flow constructs due to the ordering chosen by the loop structure for its
internal storage. This change removes a completely wasteful vector of
basic blocks, saving memory allocation in the common case even though it
costs us CPU in the fairly rare case of unnatural loops. Finally, it
fixes the latest crasher reduced out of GCC's single source. Thanks
again to Benjamin Kramer for the reduction, my bugpoint skills failed at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144627 91177308-0d34-0410-b5e6-96231b3b80d8

Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Support/Compiler.h: Invalidate LLVM_ATTRIBUTE_WEAK on cygming for now.

It triggers generating insane executables with both binutils-2.19.1(msysgit) and 2.22.51.20111013(cygwin).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144621 91177308-0d34-0410-b5e6-96231b3b80d8

Really fix test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144613 91177308-0d34-0410-b5e6-96231b3b80d8

Allow for depencendy-breaking instructions before cvt*.

This should unbreak clang-x86_64-darwin10-RA, but I can't actually
reproduce the failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144611 91177308-0d34-0410-b5e6-96231b3b80d8

Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8

Move WEAK marking to the declaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144603 91177308-0d34-0410-b5e6-96231b3b80d8

Break false dependencies before partial register updates.

Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8

Track register ages more accurately.

Keep track of the last instruction to define each register individually
instead of per DomainValue.  This lets us track more accurately when a
register was last written.

Also track register ages across basic blocks.  When entering a new
basic block, use the least stale predecessor def as a worst case
estimate for register age.

The register age is used to arbitrate between conflicting domains. The
most recently defined register wins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144601 91177308-0d34-0410-b5e6-96231b3b80d8

Add ObjCPropertyDebugInfo.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144600 91177308-0d34-0410-b5e6-96231b3b80d8

Document debug info support  for objective-c properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144599 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144598 91177308-0d34-0410-b5e6-96231b3b80d8

Fix linking for some users who already have tsan enabled code and are trying to
link it against llvm code, by making our definitions weak. "Some users."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144596 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing datatype suffix variants for non-writeback VST1 instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing datatype suffix variants for non-writeback VLD1 instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8

Add explanatory comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144589 91177308-0d34-0410-b5e6-96231b3b80d8

Split out the plain '.{8|16|32|64}' suffix handling.

Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144588 91177308-0d34-0410-b5e6-96231b3b80d8

ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8

Supporting inline memmove isn't going to be worthwhile.  The only way to avoid
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144585 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VLDR/VSTR instructions don't need a size suffix.

Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor capture tracking (which already had a couple flags for whether returns
and stores capture) to permit the caller to see each capture point and decide
whether to continue looking.

Use this inside memdep to do an analysis that basicaa won't do. This lets us
solve another devirtualization case, fixing PR8908!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144580 91177308-0d34-0410-b5e6-96231b3b80d8

Add newline to end of file.  Thanks, Eli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144579 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for inlining small memcpys.
rdar://10412592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a performance regression from r144565. Positive offsets were being lowered
into registers, rather then encoded directly in the load/store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing type suffix options for VLDR/VSTR.

rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8