phy: rockchip-inno-usb2: add host-port support for rk322x SoC

This adds support host-port on rk322x SoC and amend phy Documentation.

Change-Id: I440adc10e25c98cbe220275fecd12774c08d24d1
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

video: rockchip: vpu: support VDPU at RK3328

The VDPU at RK3328 is a standalone decoder IP without
encoder. Also there is the other AVS+ decoder IP,
working as the combo IP.

I introduce the following commit from develop-3.10,
commit ee2f9f6912fb ("rk322xh/vcodec: bugfix, avoid combo device overwrite irq status")
commit 568dabeb12ef ("rockchip/vcodec: bugfix, inconsistence power on/off operation")

The following patches have not been introduced,
it would effect RKV device:
commit b8a2ce7e5b60 ("rockchip/vcodec: disable power-save optimization for hw defeat")
commit 046faf9ba20a ("rk322xh/vcodec: bugfix, probe failed when ion cma heap undefined")
commit beaeb230cbf2 ("rk322xh/vcodec: revise for rk322xh feature")

Change-Id: Ifc14daa84b692f8fcfbd4f6690ed66dd56bbbe29
Signed-off-by: Randy Li <randy.li@rock-chips.com>

video: rockchip: vpu: add avs decoder table

This table would be used for both AVS and AVS+ decoder.

Change-Id: I9557a3d170943a3b544d97b6c63f02679bd7b532
Signed-off-by: Randy Li <randy.li@rock-chips.com>

video: rockchip: vpu: only use the dev_mode for combo

The most of device can get this its running type from the
compatible. This property becomes unnecessary.

Change-Id: I40ec41b130fac2cadd47d92332d27c58a8c2c9f7
Signed-off-by: Randy Li <randy.li@rock-chips.com>

PM / devfreq: rockchip_dmc: add mutex lock for pmu register

As dmc may also assess register PMU_BUS_IDLE_REQ, we should prevent
pd driver and dmc driver assessing this register at the same time.

Change-Id: I546033536c87dcf497774cbc6c8f36a3e651ff07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

soc: rockchip: power-domain: export rockchip_pm_register_notify_to_dmc

This function registers a notifier to dmc devfreq, it will lock the mutex
of pmu when scaling frequency, so that pd driver and dmc driver will not
assess register PMU_BUS_IDLE_REQ at the same time.

Change-Id: I0ba96599d9050d11924d032146e6b4d415629614
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

dmaengine: pl330: fix error message to dev_err_ratelimited

Change-Id: I4d1191f5b7d330c2786eaac42213b4d255b05db8
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

ARM64: dts: rk3368-p9: enable route mipi

Change-Id: Ib93918524c173bce1283b0001e0f8ca91594dc6f
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

PM / devfreq: rockchip_dmc: set polling_ms to 50

In order to scaling frequency more timely, reduce the polling_ms.

Change-Id: Icbee5552396fa0552fb514d92ea77687228c3e28
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

PM / devfreq: rockchip_dmc: add support for rk3368

This adds the necessary data for handling dmcfreq on the rk3368.

Change-Id: Ie202cbaa3b27e52b22a5efc57c6e108fbd03a20a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

PM / devfreq: rockchip_dmc: separate the initialized code of dram

It will be easy to compatible with more rockchip platforms,
if move the initialized code of dram into a separated function.

Change-Id: Iad8738b2c0995712723a8e3e84f12ae6b9b2aa91
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

camera: rockchip: camsys_drv: 0.0x21.0xe

1) correct mipiphy_hsfreqrange of 3368.
2) add csi-phy timing setting for 3368.

Change-Id: Ia5203dcd8f01bc8989d5bb41a1b2af71bb91f607
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>

arm64: dts: rockchip: fix uart3 pinctrl error of rk3368

Change-Id: Ie62fd4c6cf1a9c38a1793c9ccd0085c91f38f438
Signed-off-by: Zorro Liu <lyx@rock-chips.com>

drm/rockchip: rga: use DMA_BIDIRECTIONAL

In some cases, we need to read data from RGA
and DMA_TO_DEVICE are not a proper flag
So change to DMA_BIDIRECTIONAL

Change-Id: I9d421e8a15f948fcb6643addab558803247ea161
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

arm: dts: rk3288: remove assinged parent for NPLL/GPLL

Change-Id: I6ab7dff4d886a776677331f370d9632363abaa87
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

arm: dts: add the basic dt file for rk3229-echo-v10

Initial support for rk3229-echo board.

Change-Id: I7587d333f296f66727bf1c686911cfca2f3c5619
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

arm: dts: add android dtsi for rk322x SoC

Change-Id: I400ab97db9d333d53474978bb339ce2ed8a99ed4
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

clk: rockchip: rk3228: fix up the clk cpu setting

support more cpu freq
add armcore div setting

Change-Id: I46ab974da763bab2e887377848be1d9049a1568f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

arm: dts: rk3228: add some assigned-clocks

Change-Id: I257bbfe5ccea74245a6fe3269a896ab968a34c4f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3228: Perfect clock description

1 Add some necessary clk ID.
2 some clks add CLK_IGNORE_UNUSED flag
3 add some critical clk

Change-Id: If52699b4d5f430413b06084b7d21fb1afd4539dd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3288: add ddrc clock support

Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.

Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: add SCLK_DDRCLK id for rk3288 ddrc

Add the needed id for the ddr clock.

Change-Id: I9578decd2348a35a6e9c4cc3527375d4d02a2af6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

arm64: dts: rockchip: Rename OPP nodes as opp-<opp-hz>

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.

Change-Id: I5748be7888db149633c3980c3f5e9715cd256a52
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

ARM: dts: rk3288: Rename OPP nodes as opp-<opp-hz>

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.

Change-Id: Id239f49618a818ad87bb77e99f52b52a5ee2dbc6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

iio: adc: remove unused rockchip_adc driver

replaced by rockchip_saradc from upstream.

Change-Id: I1a0a54240cd4b6f647a84597c739669b7c829157
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm/rockchip: vop: fix update timeout to 1000 ms

Extend timeout value from 100 jiffies to 1000 millisecond.

Change-Id: I4941bb487051a73cf348f72799226e17d4b60e49
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

camera: rockchip: camsys driver 0.0x21.d

modify mipiphy_hsfreqrange for 3368

Change-Id: I4a9d2d6a28202e734e900f3bb761190842c2948e
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>

drm/rockchip: vop: fix NV12 video display error

fixup the scale calculation formula on the case
src_height == (dst_height/2).

Change-Id: I620a4646232c016ff1547b5b6469ed2eedeacfed
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

drm: bridge: dw-hdmi: Reorder HDMI Initialization Step

There is a bug of pll lock detection in previous code.

/* Wait for PHY PLL lock */
msec = 5;
do {
val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
if (!val)
break;
...
} while (1)

while is break if pll is not lock yet, the real lock status may
be after the dw_hdmi_enable_video_path.

This bug is fixed in commit <a479fa5417b12fdf7aef8e41fdb99393e1c28581>
(FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power up sequence)

But it introduced an new bug: hdmi output timing may be not stable,
the format shown on some TV is not a standard hdmi timing. For example,
1080P will be shown as 1922x1080 on LEADSTAR LD-1088.

After reorder the HDMI Initialization Step, phy initialization is
moved after the dw_hdmi_enable_video_path, this bug is fixed.

Change-Id: Id996978ceabcf1cce4bf83ddb84528c04fbb7583
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm: bridge: dw-hdmi: remove the function is_rockchip

The function is_rockchip isn't used any more now that phy reset
operation is performed based on detected phy type.

Change-Id: I58e7a222bc1e1578f0d5d2fcd884b17171fb9601
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

drm: bridge: dw-hdmi: add default phy function for DW_HDMI_PHY_DWC_HDMI20_TX_PHY

DWC HDMI 2.0 TX PHY has the same register layout with DWC HDMI
MHL TX PHY, so we use hdmi_phy_configure_dwc_hdmi_3d_tx as
DW_HDMI_PHY_DWC_HDMI20_TX_PHY default configuration function.

Change-Id: Ib50464b9eef87707a8597493cc05e61a1ecde240
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>

FROMLIST: drm: bridge: dw-hdmi: Add support for custom PHY configuration

The DWC HDMI TX controller interfaces with a companion PHY. While
Synopsys provides multiple standard PHYs, SoC vendors can also integrate
a custom PHY.

Modularize PHY configuration to support vendor PHYs through platform
data. The existing PHY configuration code was originally written to
support the DWC HDMI 3D TX PHY, and seems to be compatible with the DWC
MLP PHY. The HDMI 2.0 PHY will require a separate configuration
function.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <Jose.Abreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-8-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I7527e77fd8679434379161a6bf3daa1639d081b8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9603303/)

fiq_debugger: use __handle_sysrq instead of handle_sysrq

Because init.rc does the following operation, handle_sysrq
will do nothing. If we want to use sysrq, __handle_sysrq
can work.
write /proc/sys/kernel/sysrq 0

Change-Id: Ia51debd92f393326f183736e405e25dc4d6a2abc
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

drivers: switch: clear drvdata before device_destroy

Otherwise, we see write after free.

=============================================================================
BUG kmalloc-1024 (Not tainted): Poison overwritten
-----------------------------------------------------------------------------

INFO: 0xc599bcc4-0xc599bcc7. First byte 0x0 instead of 0x6b
INFO: Allocated in device_create_groups_vargs+0x34/0xcc age=43 cpu=3 pid=1
kmem_cache_alloc_trace+0xd8/0x378
device_create_groups_vargs+0x34/0xcc
device_create_vargs+0x20/0x28
device_create+0x28/0x48
switch_dev_register+0x80/0x108
dw_hdmi_bind+0x38c/0x9e4
dw_hdmi_rockchip_bind+0x248/0x38c
component_bind_all+0x78/0x1e4
rockchip_drm_bind+0x1bc/0xbc0
try_to_bring_up_master.part.0+0xa8/0x138
component_master_add_with_match+0xb8/0x100
rockchip_drm_platform_probe+0x188/0x1d0
platform_drv_probe+0x50/0xa0
driver_probe_device+0x110/0x2c0
__driver_attach+0x70/0x94
bus_for_each_dev+0x94/0xc0
INFO: Freed in device_release+0x5c/0x90 age=42 cpu=3 pid=1
device_release+0x5c/0x90
kobject_release+0xd4/0x11c
device_destroy+0x2c/0x38
switch_dev_unregister+0x30/0x5c
dw_hdmi_unbind+0x48/0xc8
component_bind_all+0x1a4/0x1e4
rockchip_drm_bind+0x1bc/0xbc0
try_to_bring_up_master.part.0+0xa8/0x138
component_master_add_with_match+0xb8/0x100
rockchip_drm_platform_probe+0x188/0x1d0
platform_drv_probe+0x50/0xa0
driver_probe_device+0x110/0x2c0
__driver_attach+0x70/0x94
bus_for_each_dev+0x94/0xc0
bus_add_driver+0xcc/0x1e8
driver_register+0x9c/0xe0

Change-Id: Ied903eed40212e9666e123dd3f69a2a2966b6bb5
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>

drm: bridge/dw-hdmi: fix 4 block edid read error

msgs[0].addr will be 0x30 when read edid with more than 2 block.
but still a read edid operation with write DDC_ADDR to
HDMI_I2CM_SLAVE register.So fix it.

Change-Id: I5f0cd9172acd4a68d5b54eaf99f17b45385a4263
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

video: rockchip: vop: 3399: fix bt709 to bt2020 csc error

Change-Id: I073c2dbb6693885a3c75c9ca476879544ec15349
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video/rockchip: rga2: do some check for user memory

Change-Id: Idbf3d918f127ad53e2d05e56fadcf0b7a4fea2b4
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video/rockchip: rga2: fix error page on cache flush

Change-Id: Ic23e0f6c25f68c28a87f4e4ef459bda56d4990ba
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

firmware: rockchip: deliver sip implement version v2 to optee

Because optee works on both kernel 3.10 and 4.4, these two branches
have different rockchip sip protocol that sip version v1 for 3.10
and sip version v2 for 4.4

Change-Id: I4f69352d2001b1c22c5617dc443510263b4c53f5
Signed-off-by: chenjh <chenjh@rock-chips.com>

gpio: rk8xx: print probe successful info

because gpio framework doesn't print any related info

Change-Id: I2325270027210432cd31d1cec6caf19770363705
Signed-off-by: chenjh <chenjh@rock-chips.com>

FROMLIST: drm: bridge: dw-hdmi: Create PHY operations

The HDMI TX controller support different PHYs whose programming
interface can vary significantly, especially with vendor PHYs that are
not provided by Synopsys. To support them, create a PHY operation
structure that can be provided by the platform glue layer. The existing
PHY handling code (limited to Synopsys PHY support) is refactored into a
set of default PHY operations that are used automatically when the
platform glue doesn't provide its own operations.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170305233615.11993-1-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Id865ebee71f2a34e12456d721f8b237204ea9f7e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9604819/)

FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power up sequence

When powering the PHY up we need to wait for the PLL to lock. This is
done by polling the TX_PHY_LOCK bit in the HDMI_PHY_STAT0 register
(interrupt-based wait could be implemented as well but is likely
overkill). The bit is asserted when the PLL locks, but the current code
incorrectly waits for the bit to be deasserted. Fix it, and while at it,
replace the udelay() with a sleep as the code never runs in
non-sleepable context.

To be consistent with the power down implementation move the poll loop
to the power off function.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170305233557.11945-1-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Ibdbb87b7474a6137698692480f11ee61cd429f8e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9604815/)

FROMLIST: drm: bridge: dw-hdmi: Fix the PHY power down sequence

The PHY requires us to wait for the PHY to switch to low power mode
after deasserting TXPWRON and before asserting PDDQ in the power down
sequence, otherwise power down will fail.

The PHY power down can be monitored though the TX_READY bit, available
through I2C in the PHY registers, or the TX_PHY_LOCK bit, available
through the HDMI TX registers. As the two are equivalent, let's pick the
easier solution of polling the TX_PHY_LOCK bit.

The power down code is currently duplicated in multiple places. To avoid
spreading multiple calls to a TX_PHY_LOCK poll function, we have to
refactor the power down code and group it all in a single function.

Tests showed that one poll iteration was enough for TX_PHY_LOCK to
become low, without requiring any additional delay. Retrying the read
five times with a 1ms to 2ms delay between each attempt should thus be
more than enough.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170305233539.11898-1-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I64dadab663b34800d4fe3fe4fd9cd4fb029e2ce3
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9604811/)

FROMLIST: drm: bridge: dw-hdmi: Enable CSC even for DVI

If the input pixel format is not RGB, the CSC must be enabled in order to
provide valid pixel to DVI sinks.
This patch removes the hdmi only dependency on the CSC enabling.

Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-4-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I7e9da663158790f7a84e126c6ed8b763a262bd1f
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9603293/)

FROMLIST: drm: bridge: dw-hdmi: Move CSC configuration out of PHY code

The color space converter isn't part of the PHY, move its configuration
out of PHY code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-3-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Ieea06dcb4a73e77e183901206014a42a4e6a460d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9603291/)

UPSTREAM: drm: bridge: dw-hdmi: Assert SVSRET before resetting the PHY

According to the PHY IP core vendor, the SVSRET signal must be asserted
before resetting the PHY. Tests on RK3288 and R-Car Gen3 showed no
regression, the change should thus be safe.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-20-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I41d4ae5fe19266c430589a254ed1e44120d30ee8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 2668db37888ff63282147b00dcf54fa491831df3)

UPSTREAM: drm: bridge: dw-hdmi: Fix the name of the PHY reset macros

The PHY reset signal is controlled by bit PHYRSTZ in the MC_PHYRSTZ
register. The signal is active low on Gen1 PHYs and active high on Gen2
PHYs. The driver toggles the signal high then low, which is correct for
all currently supported platforms, but the register values macros are
incorrectly named. Replace them with a single macro named after the bit,
and add a comment to the source code to explain the behaviour.

The driver's behaviour isn't changed by this rename, the code will still
need to be fixed to support Gen1 PHYs.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-19-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I61a1185dc2528f6be61a3f250902445b92217365
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 54d72737b098f3597c57693e1aa96699a21b11fe)

UPSTREAM: drm: bridge: dw-hdmi: Define and use macros for PHY register addresses

Replace the hardcoded register address numerical values with macros to
clarify the code.

This change has been tested by comparing the assembly code before and
after the change.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-18-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I131045008e021218f1338592999ba4de33fc0883
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from f0e7f2f3b6333a02dd7cb89822e6330631c9a3e3)

UPSTREAM: drm: bridge: dw-hdmi: Detect PHY type at runtime

Detect the PHY type and use it to handle the PHY type-specific SVSRET
signal.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-17-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I6f128e5e513e68a4e42a6161d7cd55721a748dc8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from faba6c3cff177689aec132291b1cf537831d9a2e)

UPSTREAM: drm: bridge: dw-hdmi: Handle overflow workaround based on device version

Use the device version queried at runtime instead of the device type
provided through platform data to handle the overflow workaround. This
will make support of other SoCs integrating the same HDMI TX controller
version easier.

Among the supported platforms only i.MX6DL and i.MX6Q have been
identified as needing the workaround. Disabling it on Rockchip RK3288
(which integrates a v2.00a controller) didn't produce any error or
artifact.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-16-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I42f48df6f8509724d049e93b05a48fe0de8207f2
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from be41fc55f1aa3c9ae0eb9e0b384db5150eca055f)

UPSTREAM: drm: bridge: dw-hdmi: Detect AHB audio DMA using correct register

Bit 0 in CONFIG1_ID tells whether the IP core uses an AHB slave
interface for control. The correct way to identify AHB audio DMA support
is through bit 1 in CONFIG3_ID.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-15-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Iafac3a0d301fdd8e8a217da3c9a49b829cdd2edc
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 0c674948b7f4e4ffc19ba5af65a274e945c0c689)

UPSTREAM: drm: bridge: dw-hdmi: Reject invalid product IDs

The DWC HDMI TX can be recognized by the two product identification
registers. If the registers don't read as expect the IP will be very
different than what the driver has been designed for, or will be
misconfigured in a way that makes it non-operational (invalid memory
address, incorrect clocks, ...). We should reject this situation with an
error.

While this isn't critical for proper operation with supported IPs at the
moment, the driver will soon gain automatic device-specific handling
based on runtime device identification. This change makes it easier to
implement that without having to default to a random guess in case the
device can't be identified.

While at it print a readable version number in the device identification
message instead of raw register values.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-14-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Iaa8e17429e9b4033f97b2bf49504e6f390ce7c44
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 0527e12e8264ae96b1fcc550b4a9e5940f4ffc30)

UPSTREAM: drm: bridge: dw-hdmi: Rename CONF0 SPARECTRL bit to SVSRET

The bit is documented in a Rockchip BSP as

 #define m_SVSRET_SIG (1 << 5) /* depend on PHY_MHL_COMB0=1 */

This is confirmed by a Renesas platform, which uses a 2.0 DWC HDMI TX as
the RK3288. Rename the bit accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-13-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Ib9cd213b8bc956169cf3d3e13415d99a4c65717c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from f4104e8fe12c173fbba5e7e30b846e09eeb5bfbd)

UPSTREAM: drm: bridge: dw-hdmi: Remove PHY configuration resolution parameter

The current code hard codes the call of hdmi_phy_configure() to be 8bpp
and provides extraneous error checking to verify that this hardcoded
value is correct. Simplify the implementation by removing the argument.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-12-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I45ce56616a06d322c5f5fb9e9d01971e65bcf23c
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 1acc6bdeee1ef2ecac3ba070a403827ab8f16be5)

UPSTREAM: drm: bridge: dw-hdmi: Don't forward HPD events to DRM core before attach

Hotplug events should only be forwarded to the DRM core by the interrupt
handler when the bridge has been attached, otherwise the DRM device
pointer will be NULL, resulting in a crash.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-7-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Ic1387b5253d4586774cdb82e089effdd4104e380
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from ba5d7e6160b7aed4df92d1764aa90790db0e7996)

UPSTREAM: drm: bridge: dw-hdmi: Embed drm_bridge in struct dw_hdmi

The drm_bridge instance is always needed, there's no point in allocating
it separately.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-5-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Iba5ca73877c3611148af51c0993276eac982bb3e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from 70c963ec4f15a13197524611875168f23acc4a97)

UPSTREAM: drm: bridge: dw-hdmi: Remove unused function parameter

The 'prep' parameter passed to hdmi_phy_configure() is useless. It is
hardcoded as 0, and if set, simply prevents the configure function from
executing.

Remove it.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-4-laurent.pinchart+renesas@ideasonboard.com
Change-Id: Iff93b8a109d5540283f8ad39ef25ce2fd79acb2a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from dfa73065d61b6ce57aed90bb0d745c4b6f5b71e7)

UPSTREAM: drm: bridge: dw-hdmi: Merge __hdmi_phy_i2c_write and hdmi_phy_i2c_write

The latter is just an int wrapper around the former void function that
unconditionally returns 0. As the return value is never checked, merge
the two functions into one.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-2-laurent.pinchart+renesas@ideasonboard.com
Change-Id: I2b994874fac9869c951a30c8328df883c0bb7821
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
(cherry pick from cc7e96232763ff33418b088b436a564441347b15)

video/rockchip: rga2: fixup high memory cache flush

Change-Id: I6e2e12e19aaa7c5bf9187dc5ec268626ecd4069f
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video: rockchip: vop: 3399: add more format support for gather

Change-Id: I790c16604b40775c228434cd2cdbb1f48bb8ee5e
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

ARM64: dts: rk3368-android: update route state

1. add lvds node to /display_subsystem;
2. set route_mipi state to closed at rk3368-android.dtsi
3. set route_mipi state to okay at rk3368-sheep.dts

Change-Id: I8052e38764f85f700014ea40b208b38c09cae56b
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: dts: rockchip: rk3368: add pinctrl for lvds ttl mode

Change-Id: I5a6aa463142ccb6955c2380ca30795d2790e6124
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

drm/rockchip: lvds: add support rk3368 lvds

Change-Id: I288fd42d9591119fadcbede67ff74be52d594e02
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

drm/rockchip: analogix_dp: add supports for regulators in edp IP

I found if eDP_AVDD_1V0 and eDP_AVDD_1V8 are not been power at
RK3288, once trying to enable the pclk clock, the kernel would dead.
This patch would try to enable them first.

The eDP_AVDD_1V8 is used for eDP phy, and the eDP_AVDD_1V0 are used
both for eDP phy and controller.

Change-Id: I4e8a34609d5b292d7da77385ff15bebbf258090c
Signed-off-by: Randy Li <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>

MALI: fix thermal crash with booting up

If the temperature(sbs-battery) reaches the switch_on_temp, it would try
to calculate requested power of all thermal instances. Then hit the
crash[0] caused by the gpu thermal sensor, since the thermal driver had not
registered in time.

[0]
[    0.827943] Call trace:
[    0.827953] [<          (null)>]           (null)
[    0.827969] [<ffffffc00070af1c>] get_static_power+0xd8/0xe8
[    0.827981] [<ffffffc00070b190>] devfreq_cooling_get_requested_power+0x94/0x170
[    0.827997] [<ffffffc0007094c8>] power_allocator_throttle+0x270/0x804
..

Change-Id: I63f66e54d69115165a7b3ec798b9009c360daa62
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

video: rockchip: vop full: fix vop operation error after shutdown

Change-Id: Ia3baf781e3e829fb906a856c6e73d0b02a4437eb
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

video: rockchip: rga2: delay rga2 initcall

rga2 and edp pd is the same -- PD_VIO.
if rga2 initcall earlier than edp,
then it will flash sreen when power on.

Change-Id: Ifa9b4f1f985a6de66d48915f56bc7d225ae0d7a9
Signed-off-by: xubilv <xbl@rock-chips.com>

FROMLIST: ARM: dts: rockchip: Add support for PCM-947 carrier board

Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.

Following interfaces and devices are available on the PCM-947 carrier board:

  - 2x UART
  - micro SDMMC
  - USB host and USB otg
  - USB 3503 HSIC hub
  - Ethernet
  - 2nd alternative KSZ9031 ethernet phy
  - Display connectors: PHYTEC LVDS, DDG LVDS, parallel signals, HDMI
  - Parallel Camera CIF
  - SGTL5000-32QFN audio codec
  - 4x LEDs connected via PCA9533
  - 2 user buttons
  - Expansion connectors for WiFi and other modules
  - RTC RV-4162-C7
  - Resistive touch STMPE811
  - EEPROM M24C32

(am from https://patchwork.codeaurora.org/patch/217711/)
Change-Id: Iab737032fa74e5fecc49ff6d06d27cc952ff1a6f
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

FROMLIST: ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM

The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:

  - 1 GB DDR3 RAM (2 Banks)
  - 1x 4 KB EEPROM
  - DP83867 Gigabit Ethernet PHY
  - 16 MB SPI Flash
  - 4 GB eMMC Flash

(am from https://patchwork.codeaurora.org/patch/217709/)
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Change-Id: Id1155a479dfcddfaeb870461de79855c6680db9c
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

driver: rk nand: update ftl to support slc nand

    1. support arm v7.
    2. support 128MB and 256MB SLC NAND FLASH.

Change-Id: I3b2972ed27c138ed7a6c75e2fefa10ce06a5b668
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

ARM64: rockchip_cros_defconfig: remove nand deconfig

Change-Id: Ib84e31b79ed88a24d74a1280d7859296a4d76e3d
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>

firmware: rockchip: rename 'sip_smc_ddr_cfg' to 'sip_smc_dram'

Change-Id: I07767d9eb26194c04fd4e3f92e8ae24b47621c5a
Signed-off-by: chenjh <chenjh@rock-chips.com>

FROMLIST: usb: gadget: f_fs: avoid out of bounds access on comp_desc

Companion descriptor is only used for SuperSpeed endpoints,
if the endpoints are HighSpeed or FullSpeed, the Companion
descriptor will not allocated, so we can only access it if
gadget is SuperSpeed.

I can reproduce this issue on Rockchip platform rk3368 SoC
which supports USB 2.0, and use functionfs for ADB. Kernel
build with CONFIG_KASAN=y and CONFIG_SLUB_DEBUG=y report
the following BUG:

==================================================================
BUG: KASAN: slab-out-of-bounds in ffs_func_set_alt+0x224/0x3a0 at addr ffffffc0601f6509
Read of size 1 by task swapper/0/0
============================================================================
BUG kmalloc-256 (Not tainted): kasan: bad access detected
----------------------------------------------------------------------------

Disabling lock debugging due to kernel taint
INFO: Allocated in ffs_func_bind+0x52c/0x99c age=1275 cpu=0 pid=1
alloc_debug_processing+0x128/0x17c
___slab_alloc.constprop.58+0x50c/0x610
__slab_alloc.isra.55.constprop.57+0x24/0x34
__kmalloc+0xe0/0x250
ffs_func_bind+0x52c/0x99c
usb_add_function+0xd8/0x1d4
configfs_composite_bind+0x48c/0x570
udc_bind_to_driver+0x6c/0x170
usb_udc_attach_driver+0xa4/0xd0
gadget_dev_desc_UDC_store+0xcc/0x118
configfs_write_file+0x1a0/0x1f8
__vfs_write+0x64/0x174
vfs_write+0xe4/0x200
SyS_write+0x68/0xc8
el0_svc_naked+0x24/0x28
INFO: Freed in inode_doinit_with_dentry+0x3f0/0x7c4 age=1275 cpu=7 pid=247
...
Call trace:
[<ffffff900808aab4>] dump_backtrace+0x0/0x230
[<ffffff900808acf8>] show_stack+0x14/0x1c
[<ffffff90084ad420>] dump_stack+0xa0/0xc8
[<ffffff90082157cc>] print_trailer+0x188/0x198
[<ffffff9008215948>] object_err+0x3c/0x4c
[<ffffff900821b5ac>] kasan_report+0x324/0x4dc
[<ffffff900821aa38>] __asan_load1+0x24/0x50
[<ffffff90089eb750>] ffs_func_set_alt+0x224/0x3a0
[<ffffff90089d3760>] composite_setup+0xdcc/0x1ac8
[<ffffff90089d7394>] android_setup+0x124/0x1a0
[<ffffff90089acd18>] _setup+0x54/0x74
[<ffffff90089b6b98>] handle_ep0+0x3288/0x4390
[<ffffff90089b9b44>] dwc_otg_pcd_handle_out_ep_intr+0x14dc/0x2ae4
[<ffffff90089be85c>] dwc_otg_pcd_handle_intr+0x1ec/0x298
[<ffffff90089ad680>] dwc_otg_pcd_irq+0x10/0x20
[<ffffff9008116328>] handle_irq_event_percpu+0x124/0x3ac
[<ffffff9008116610>] handle_irq_event+0x60/0xa0
[<ffffff900811af30>] handle_fasteoi_irq+0x10c/0x1d4
[<ffffff9008115568>] generic_handle_irq+0x30/0x40
[<ffffff90081159b4>] __handle_domain_irq+0xac/0xdc
[<ffffff9008080e9c>] gic_handle_irq+0x64/0xa4
...
Memory state around the buggy address:
  ffffffc0601f6400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  ffffffc0601f6480: 00 00 00 00 00 00 00 00 00 00 06 fc fc fc fc fc
 >ffffffc0601f6500: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
                       ^
  ffffffc0601f6580: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
  ffffffc0601f6600: fc fc fc fc fc fc fc fc 00 00 00 00 00 00 00 00
==================================================================

(am from https://patchwork.kernel.org/patch/9697795/)
Change-Id: Ic27fc44663f51e139825cb36ca16e4b315293fe2
Signed-off-by: William Wu <william.wu@rock-chips.com>

drm/rockchip: vop: fix vtotal calc mistake on interlace mode

Change-Id: I820d439735dddeaaa5db5fc75356e242a9d77656
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rk3368-android: add route_hdmi node

Change-Id: I6fa418e383a62488576b0f89186c36078814a2ed
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm64: dts: rk3368: Add hdmi support

Change-Id: I6d0ff68e2fbd852ae796e73de30e5cd577e924ed
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

drm/rockchip: dw_hdmi: Add support for rk3368

Change-Id: I6a49447a5edd53013ed81875f351089793914f77
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm64: dts: rk3368-android: remove hdmi node

Change-Id: I4e775f5d47c003feea730437a046761f5f4569b2
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

arm64: dts: rk3368-sheep: disable hdmi

Change-Id: Ie2e8b5e9d312cfc8efed1c19bac118de31458f51
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

video: rockchip: fb: add fb ser par support 4k output

Change-Id: Iad0a49b9b3f0f49c2bc71e8ed73fade1106b57ac
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

arm64: dts: rk3368: add 'leakage-scaling-sel' property for cluster1_opp

Change-Id: Icabe3cc278161010d638b4d3e231557246075b0a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

cpufreq: rockchip: parse 'leakage-scaling-sel'

Change-Id: Ia473f960dbf0d1cc6c68fdd0e67b1d5cd8ddfa17
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: Add adaptive frequency scaling for pll_rk3066

Change-Id: I9c3422a45f86e8b95be0ad069ac70d5490eb5161
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

hid: usbhid: enable hid to wakeup system if it supports remote wakeup

Refer to E.2 (P67) of Device Class Definition for Human Interface
Devices V1.11, the bmAttributes field of the standard configuration
descriptor bit 5 should be set if the HID support Remote Wakeup.

This patch enable the usb HID to wake up the system if the HID
supports remote wakeup.

Change-Id: I169c49ff6187b6400b91633332a72964caca1a94
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

ARM: rockchip: pm: add system suspend support for rk3288

PSCI v1.0 introduces a new API called PSCI_SYSTEM_SUSPEND. This API
provides the mechanism by which the calling OS can request entry into
the deepest possible system sleep state.

Change-Id: I2dbb56ad337315eee76170443de96a1df05f8aab
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

power: rk818-charger: fix cancel delayed work error because of not initialize

Change-Id: I2273c55f2ffbc5d09cf80bbfdf3030acada39eab
Signed-off-by: chenjh <chenjh@rock-chips.com>

video/rockchip: rga2: fix rga crash with high memory

phys_to_virt not support highmem.

[   38.247986] Unable to handle kernel paging request at virtual address 20857000
[   38.306701] pgd = ed418000
[   38.309505] [20857000] *pgd=00000000
[   38.313118] Internal error: Oops: 2805 [#1] PREEMPT SMP ARM
[   38.318682] Modules linked in:
[   38.321746] CPU: 2 PID: 1410 Comm: DisplayThread Not tainted 4.4.55 #156
[   38.328435] Hardware name: Rockchip (Device Tree)
[   38.333131] task: dd2ad480 ti: dcc08000 task.ti: dcc08000
[   38.338527] PC is at v7_dma_flush_range+0x1c/0x34
[   38.343225] LR is at rga_dma_flush_range+0x30/0x68
[   39.215229] [<c0117440>] (v7_dma_flush_range) from [<c03f969c>] (rga_dma_flush_range+0x30/0x68)
[   39.223918] [<c03f969c>] (rga_dma_flush_range) from [<c03f98f4>] (rga2_MapUserMemory+0x220/0x2b0)
[   39.232777] [<c03f98f4>] (rga2_MapUserMemory) from [<c03f9bd4>] (rga2_set_mmu_info+0x1bc/0x928)
[   39.241461] [<c03f9bd4>] (rga2_set_mmu_info) from [<c03f8930>] (rga2_blit+0x2f4/0x448)
[   39.249366] [<c03f8930>] (rga2_blit) from [<c03f8ae8>] (rga2_blit_sync+0x64/0x1b0)
[   39.256923] [<c03f8ae8>] (rga2_blit_sync) from [<c03f91dc>] (rga_ioctl+0x4d0/0x6d8)
[   39.264570] [<c03f91dc>] (rga_ioctl) from [<c023ea58>] (do_vfs_ioctl+0x564/0x6a0)
[   39.272042] [<c023ea58>] (do_vfs_ioctl) from [<c023ebe0>] (SyS_ioctl+0x4c/0x74)
[   39.279342] [<c023ebe0>] (SyS_ioctl) from [<c0107180>] (ret_fast_syscall+0x0/0x3c)

Change-Id: I81fe2d108932a96414a2822c1329c4335753d1d9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

video: rockchip: rkvdec: add a new device id

RKVDEC second generation uses a new device id.
It is the new generation of the RKV decoder found on
the RK3328 platform.

Change-Id: I63891b7f774e68d8820f1a9c88052795af37f99d
Signed-off-by: Randy Li <randy.li@rock-chips.com>

thermal: rockchip: rk3368: fix bad unlock balance issue

We WRONGLY supposed both REGULATOR_EVENT_PRE_VOLTAGE_CHANGE and
REGULATOR_EVENT_VOLTAGE_CHANGE were used in pairs. If volts are
not changed in volts setting process, REGULATOR_EVENT_PRE_VOLTAGE_CHANGE
is NOT sent,but REGULATOR_EVENT_VOLTAGE_CHANGE is sent. So we check the
lock status before we release the lock.

[    3.535657] =====================================
[    3.535703] [ BUG: bad unlock balance detected! ]
[    3.535757] 4.4.55 #2 Not tainted
[    3.535800] -------------------------------------
[    3.535847] cfinteractive/65 is trying to release lock (thermal_reg_mutex) at:
[    3.535969] [<ffffff8008c23ca4>] mutex_unlock+0xc/0x14
[    3.536015] but there are no more locks to release!
[    3.536058] wifi_platform_bus_enumerate device present 1
[    3.536076]
[    3.536076] other info that might help us debug this:
[    3.536088] ======== Card detection to detect SDIO card! ========
[    3.536104] 4 locks held by cfinteractive/65:
[    3.536115] mmc2:mmc host rescan start!
[    3.536123]  #0:  (&policy->rwsem){+.+.+.}, at: [<ffffff8008829734>] cpufreq_interactive_speedchange_task+0x138/0x48c
[    3.536323]  #1:  (&pcpu->enable_sem){++++..}, at: [<ffffff8008829740>] cpufreq_interactive_speedchange_task+0x144/0x48c
[    3.536510]  #2:  (&rdev->mutex){+.+.+.}, at: [<ffffff8008472948>] regulator_set_voltage+0x34/0x90
[    3.536700]  #3:  (&(&rdev->notifier)->rwsem){.+.+..}, at: [<ffffff80080c0558>] __blocking_notifier_call_chain+0x30/0x64
[    3.536892]
[    3.536892] stack backtrace:
[    3.536962] CPU: 2 PID: 65 Comm: cfinteractive Not tainted 4.4.55 #2
[    3.537011] Hardware name: Rockchip rk3368 p9 board (DT)
[    3.537056] Call trace:
[    3.537118] [<ffffff8008088a4c>] dump_backtrace+0x0/0x1c4
[    3.537182] [<ffffff8008088c24>] show_stack+0x14/0x1c
[    3.537249] [<ffffff80083ada90>] dump_stack+0xa8/0xe0
[    3.537317] [<ffffff8008186c04>] print_unlock_imbalance_bug.part.25+0xbc/0xcc
[    3.537386] [<ffffff80080f8210>] lock_release+0x218/0x464
[    3.537448] [<ffffff8008c23c1c>] __mutex_unlock_slowpath+0xf4/0x170
[    3.537507] [<ffffff8008c23ca4>] mutex_unlock+0xc/0x14
[    3.537573] [<ffffff800880510c>] rk3368_thermal_notify+0x5c/0x68
[    3.537637] [<ffffff80080c0248>] notifier_call_chain+0x54/0x88
[    3.537702] [<ffffff80080c0570>] __blocking_notifier_call_chain+0x48/0x64
[    3.537768] [<ffffff80080c05a0>] blocking_notifier_call_chain+0x14/0x1c
[    3.537837] [<ffffff80084701d0>] _regulator_do_set_voltage+0x3dc/0x61c
[    3.537904] [<ffffff80084705b8>] regulator_set_voltage_unlocked+0x1a8/0x208
[    3.537971] [<ffffff8008472970>] regulator_set_voltage+0x5c/0x90
[    3.538039] [<ffffff800850708c>] _set_opp_voltage+0x44/0xa4
[    3.538104] [<ffffff8008508400>] dev_pm_opp_set_rate+0x47c/0x540
[    3.538168] [<ffffff800882be30>] set_target+0x30/0x38
[    3.538234] [<ffffff80088222e0>] __cpufreq_driver_target+0x1d8/0x298
[    3.538298] [<ffffff800882986c>] cpufreq_interactive_speedchange_task+0x270/0x48c
[    3.538360] [<ffffff80080bee1c>] kthread+0xf4/0xfc
[    3.538419] [<ffffff80080826d0>] ret_from_fork+0x10/0x40

Change-Id: I8a89bde9ff6ec83255b8a4c017e6ff792535ebb8
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>

UPSTREAM: usb: gadget: f_fs: Fix possibe deadlock

When system try to close /dev/usb-ffs/adb/ep0 on one core, at the same
time another core try to attach new UDC, which will cause deadlock as
below scenario. Thus we should release ffs lock before issuing
unregister_gadget_item().

[   52.642225] c1 ======================================================
[   52.642228] c1 [ INFO: possible circular locking dependency detected ]
[   52.642236] c1 4.4.6+ #1 Tainted: G        W  O
[   52.642241] c1 -------------------------------------------------------
[   52.642245] c1 usb ffs open/2808 is trying to acquire lock:
[   52.642270] c0  (udc_lock){+.+.+.}, at: [<ffffffc00065aeec>]
usb_gadget_unregister_driver+0x3c/0xc8
[   52.642272] c1  but task is already holding lock:
[   52.642283] c0  (ffs_lock){+.+.+.}, at: [<ffffffc00066b244>]
ffs_data_clear+0x30/0x140
[   52.642285] c1 which lock already depends on the new lock.
[   52.642287] c1
               the existing dependency chain (in reverse order) is:
[   52.642295] c0
       -> #1 (ffs_lock){+.+.+.}:
[   52.642307] c0        [<ffffffc00012340c>] __lock_acquire+0x20f0/0x2238
[   52.642314] c0        [<ffffffc000123b54>] lock_acquire+0xe4/0x298
[   52.642322] c0        [<ffffffc000aaf6e8>] mutex_lock_nested+0x7c/0x3cc
[   52.642328] c0        [<ffffffc00066f7bc>] ffs_func_bind+0x504/0x6e8
[   52.642334] c0        [<ffffffc000654004>] usb_add_function+0x84/0x184
[   52.642340] c0        [<ffffffc000658ca4>] configfs_composite_bind+0x264/0x39c
[   52.642346] c0        [<ffffffc00065b348>] udc_bind_to_driver+0x58/0x11c
[   52.642352] c0        [<ffffffc00065b49c>] usb_udc_attach_driver+0x90/0xc8
[   52.642358] c0        [<ffffffc0006598e0>] gadget_dev_desc_UDC_store+0xd4/0x128
[   52.642369] c0        [<ffffffc0002c14e8>] configfs_write_file+0xd0/0x13c
[   52.642376] c0        [<ffffffc00023c054>] vfs_write+0xb8/0x214
[   52.642381] c0        [<ffffffc00023cad4>] SyS_write+0x54/0xb0
[   52.642388] c0        [<ffffffc000085ff0>] el0_svc_naked+0x24/0x28
[   52.642395] c0
              -> #0 (udc_lock){+.+.+.}:
[   52.642401] c0        [<ffffffc00011e3d0>] print_circular_bug+0x84/0x2e4
[   52.642407] c0        [<ffffffc000123454>] __lock_acquire+0x2138/0x2238
[   52.642412] c0        [<ffffffc000123b54>] lock_acquire+0xe4/0x298
[   52.642420] c0        [<ffffffc000aaf6e8>] mutex_lock_nested+0x7c/0x3cc
[   52.642427] c0        [<ffffffc00065aeec>] usb_gadget_unregister_driver+0x3c/0xc8
[   52.642432] c0        [<ffffffc00065995c>] unregister_gadget_item+0x28/0x44
[   52.642439] c0        [<ffffffc00066b34c>] ffs_data_clear+0x138/0x140
[   52.642444] c0        [<ffffffc00066b374>] ffs_data_reset+0x20/0x6c
[   52.642450] c0        [<ffffffc00066efd0>] ffs_data_closed+0xac/0x12c
[   52.642454] c0        [<ffffffc00066f070>] ffs_ep0_release+0x20/0x2c
[   52.642460] c0        [<ffffffc00023dbe4>] __fput+0xb0/0x1f4
[   52.642466] c0        [<ffffffc00023dd9c>] ____fput+0x20/0x2c
[   52.642473] c0        [<ffffffc0000ee944>] task_work_run+0xb4/0xe8
[   52.642482] c0        [<ffffffc0000cd45c>] do_exit+0x360/0xb9c
[   52.642487] c0        [<ffffffc0000cf228>] do_group_exit+0x4c/0xb0
[   52.642494] c0        [<ffffffc0000dd3c8>] get_signal+0x380/0x89c
[   52.642501] c0        [<ffffffc00008a8f0>] do_signal+0x154/0x518
[   52.642507] c0        [<ffffffc00008af00>] do_notify_resume+0x70/0x78
[   52.642512] c0        [<ffffffc000085ee8>] work_pending+0x1c/0x20
[   52.642514] c1
              other info that might help us debug this:
[   52.642517] c1  Possible unsafe locking scenario:
[   52.642518] c1        CPU0                    CPU1
[   52.642520] c1        ----                    ----
[   52.642525] c0   lock(ffs_lock);
[   52.642529] c0                                lock(udc_lock);
[   52.642533] c0                                lock(ffs_lock);
[   52.642537] c0   lock(udc_lock);
[   52.642539] c1
                      *** DEADLOCK ***
[   52.642543] c1 1 lock held by usb ffs open/2808:
[   52.642555] c0  #0:  (ffs_lock){+.+.+.}, at: [<ffffffc00066b244>]
ffs_data_clear+0x30/0x140
[   52.642557] c1 stack backtrace:
[   52.642563] c1 CPU: 1 PID: 2808 Comm: usb ffs open Tainted: G
[   52.642565] c1 Hardware name: Spreadtrum SP9860g Board (DT)
[   52.642568] c1 Call trace:
[   52.642573] c1 [<ffffffc00008b430>] dump_backtrace+0x0/0x170
[   52.642577] c1 [<ffffffc00008b5c0>] show_stack+0x20/0x28
[   52.642583] c1 [<ffffffc000422694>] dump_stack+0xa8/0xe0
[   52.642587] c1 [<ffffffc00011e548>] print_circular_bug+0x1fc/0x2e4
[   52.642591] c1 [<ffffffc000123454>] __lock_acquire+0x2138/0x2238
[   52.642595] c1 [<ffffffc000123b54>] lock_acquire+0xe4/0x298
[   52.642599] c1 [<ffffffc000aaf6e8>] mutex_lock_nested+0x7c/0x3cc
[   52.642604] c1 [<ffffffc00065aeec>] usb_gadget_unregister_driver+0x3c/0xc8
[   52.642608] c1 [<ffffffc00065995c>] unregister_gadget_item+0x28/0x44
[   52.642613] c1 [<ffffffc00066b34c>] ffs_data_clear+0x138/0x140
[   52.642618] c1 [<ffffffc00066b374>] ffs_data_reset+0x20/0x6c
[   52.642621] c1 [<ffffffc00066efd0>] ffs_data_closed+0xac/0x12c
[   52.642625] c1 [<ffffffc00066f070>] ffs_ep0_release+0x20/0x2c
[   52.642629] c1 [<ffffffc00023dbe4>] __fput+0xb0/0x1f4
[   52.642633] c1 [<ffffffc00023dd9c>] ____fput+0x20/0x2c
[   52.642636] c1 [<ffffffc0000ee944>] task_work_run+0xb4/0xe8
[   52.642640] c1 [<ffffffc0000cd45c>] do_exit+0x360/0xb9c
[   52.642644] c1 [<ffffffc0000cf228>] do_group_exit+0x4c/0xb0
[   52.642647] c1 [<ffffffc0000dd3c8>] get_signal+0x380/0x89c
[   52.642651] c1 [<ffffffc00008a8f0>] do_signal+0x154/0x518
[   52.642656] c1 [<ffffffc00008af00>] do_notify_resume+0x70/0x78
[   52.642659] c1 [<ffffffc000085ee8>] work_pending+0x1c/0x20

Change-Id: I4ff1d8dbcaedb7df05ff26c2d8a61b153a025e88
Acked-by: Michal Nazarewicz <mina86@mina86.com>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry picked from commit b3ce3ce02d146841af012d08506b4071db8ffde3)

ARM64: rockchip: dts: re-order the nodes for RK3328 EVB

I re-order all the merged nodes in alphabetic order.

Change-Id: I677259b1ec3cd8463c8ef557a9c1f0afbef66318
Signed-off-by: Randy Li <randy.li@rock-chips.com>

net: wireless: rockchip_wlan: update bcmdhd driver 1.363.59.144

Change-Id: Ia654d6374f9be950a30adf4b912bd7df941ef532
Signed-off-by: zzc <zzc@rock-chips.com>

pinctrl: rockchip: Add rk3288 GPIO0_D0 ~ GPIO0_D7 pins support

Change-Id: If8b51cc98ea38076b4721b09a307299ac5feed0f
Signed-off-by: David Wu <david.wu@rock-chips.com>

CHROMIUM: arm64: dts: rockchip: add warm reset quirk for rk3399 dwc3

This patch adds warm reset on resume quirk for rk3399 platform.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I5d3273e9603da01395fa7cd2e2becfe350faed1d
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412489
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

CHROMIUM: usb: dwc3: add usb3_warm_reset_on_resume_quirk

This patch add a quirk for some special platforms (e.g. rk3399
platform) which need to do warm reset for USB3 device on resume.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I19acc0560001481e5a952175433e82d17dfb3a40
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412488
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

CHROMIUM: xhci: fix USB3 device undetected after resume

Some xHC controllers (e.g. Rockchip rk3399) integrated in
DWC3 IP, will be powered down in S3, and reinitialized after
resume.

However, if a USB3 device is plugged before system enter S3,
the device will be disconnected after resume because of xHC
lose power. And the device can't be detected again even if
we reinitialize xHC. In this case, CCS and CSC is '0' and
can't reflect the current state of the port, also the link
state stays in Rx.Detect.

So try to do warm reset on resume to reset USB3 device to
the default state, also reset a USB3 link, and re-exchange
link configuration information.

BUG=chrome-os-partner:58347
TEST=Plug an USB3 flash drive in rk3399 Kevin board Type-C
port, then set system enter S3. Wakeup system, check if USB3
device can be detected after resume.

Change-Id: I90975a48866569f2c2422a244afc618a3e427f57
Signed-off-by: William wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/412487
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Inno Park <ih.yoo.park@samsung.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>

arm64: dts: rk3399: sapphire-excavator: enabled pcie

Change-Id: I762ef100bf31142b4ebb359594be9c8e16cd4fc7
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>

drm: bridge: dw-hdmi: unregister the hpd workqueue when unbind

Change-Id: Ib692a4e42843a6a9c89c5a92f79a7dd85a4ae534
Signed-off-by: algea.cao <algea.cao@rock-chips.com>

video/rockchip: rga2: fix rga timeout when do scaling

rk3368 rga sometime may timeout when do scaling, and it can't
be restore until do a non-scale rga work.

So hack that, if timeout with scaling work, do a tiny non-scale rga
work before normal work.

Change-Id: I4598741347c44a1ff3c2272270f4c6a1def36177
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

arm64: dts: rockchip: sapphire-excavator: enabled hdmiin

Change-Id: I5d09ee8e07e515270fadfcdb1e8bbb98cbfaa8ac
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>