Chris Lattner [Mon, 24 May 2010 21:55:47 +0000 (21:55 +0000)]
diaggroup categories should take precedence over diag-specific groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567
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Jakob Stoklund Olesen [Mon, 24 May 2010 21:47:01 +0000 (21:47 +0000)]
Lose the dummies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564
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Jakob Stoklund Olesen [Mon, 24 May 2010 21:46:58 +0000 (21:46 +0000)]
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563
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Evan Cheng [Mon, 24 May 2010 21:33:37 +0000 (21:33 +0000)]
Avoid adding duplicate function live-in's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560
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Dan Gohman [Mon, 24 May 2010 20:51:08 +0000 (20:51 +0000)]
Fix an mmx movd encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552
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Kevin Enderby [Mon, 24 May 2010 20:32:23 +0000 (20:32 +0000)]
MC/X86: Add aliases for CMOVcc variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549
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Bob Wilson [Mon, 24 May 2010 20:08:34 +0000 (20:08 +0000)]
Clean up some extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544
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Bob Wilson [Mon, 24 May 2010 18:44:06 +0000 (18:44 +0000)]
Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531
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Devang Patel [Mon, 24 May 2010 18:26:49 +0000 (18:26 +0000)]
Do not emit line number entries for unknown debug values.
This fixes recent regression in store.exp from gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524
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Evan Cheng [Mon, 24 May 2010 18:00:18 +0000 (18:00 +0000)]
LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518
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Jakob Stoklund Olesen [Mon, 24 May 2010 17:55:38 +0000 (17:55 +0000)]
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517
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Jakob Stoklund Olesen [Mon, 24 May 2010 17:43:01 +0000 (17:43 +0000)]
Use SubRegIndex in SystemZ.
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515
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Jakob Stoklund Olesen [Mon, 24 May 2010 17:42:58 +0000 (17:42 +0000)]
SubRegIndex'ize Mips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514
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Jakob Stoklund Olesen [Mon, 24 May 2010 17:42:55 +0000 (17:42 +0000)]
SubRegIndex'ize MSP430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513
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Jakob Stoklund Olesen [Mon, 24 May 2010 17:13:28 +0000 (17:13 +0000)]
Fix a few places that depended on the numeric value of subreg indices.
Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510
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Jakob Stoklund Olesen [Mon, 24 May 2010 16:54:32 +0000 (16:54 +0000)]
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508
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Jakob Stoklund Olesen [Mon, 24 May 2010 14:48:17 +0000 (14:48 +0000)]
Rename X86 subregister indices to something shorter.
Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493
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Jakob Stoklund Olesen [Mon, 24 May 2010 14:48:12 +0000 (14:48 +0000)]
Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492
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Nicolas Geoffray [Mon, 24 May 2010 12:24:11 +0000 (12:24 +0000)]
Encode the Caml frametable by following what the comment says: the number of descriptors
is first emitted, and StackOffsets are emitted in 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488
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Duncan Sands [Mon, 24 May 2010 07:49:55 +0000 (07:49 +0000)]
Apply timeouts and memory limits in more places. In particular, when
bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104485
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Daniel Dunbar [Sun, 23 May 2010 18:36:38 +0000 (18:36 +0000)]
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104467
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Daniel Dunbar [Sun, 23 May 2010 18:36:34 +0000 (18:36 +0000)]
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104466
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Daniel Dunbar [Sun, 23 May 2010 17:44:06 +0000 (17:44 +0000)]
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463
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Bob Wilson [Sun, 23 May 2010 05:42:31 +0000 (05:42 +0000)]
VDUP doesn't support vectors with 64-bit elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455
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Daniel Dunbar [Sat, 22 May 2010 21:02:33 +0000 (21:02 +0000)]
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453
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Daniel Dunbar [Sat, 22 May 2010 21:02:29 +0000 (21:02 +0000)]
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452
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Daniel Dunbar [Sat, 22 May 2010 06:37:33 +0000 (06:37 +0000)]
MC/X86: Add alias for setz, setnz, jz, jnz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435
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John Mosby [Sat, 22 May 2010 05:13:17 +0000 (05:13 +0000)]
Trivial change to dump() function for SparseBitVector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104433
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Evan Cheng [Sat, 22 May 2010 01:47:14 +0000 (01:47 +0000)]
Implement @llvm.returnaddress. rdar://
8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421
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Jim Grosbach [Sat, 22 May 2010 01:06:18 +0000 (01:06 +0000)]
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419
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Eric Christopher [Sat, 22 May 2010 00:55:55 +0000 (00:55 +0000)]
This test is darwin only. Make it so(tm).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104418
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Bob Wilson [Sat, 22 May 2010 00:23:12 +0000 (00:23 +0000)]
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar
7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415
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Eric Christopher [Sat, 22 May 2010 00:10:22 +0000 (00:10 +0000)]
Add full bss data support for darwin tls variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414
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Devang Patel [Sat, 22 May 2010 00:04:14 +0000 (00:04 +0000)]
Collect variable information during endFunction() instead of beginFunction().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412
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Eric Christopher [Sat, 22 May 2010 00:00:58 +0000 (00:00 +0000)]
Add a new section and accessor for TLS data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411
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Bob Wilson [Fri, 21 May 2010 23:53:55 +0000 (23:53 +0000)]
Clean up extra whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410
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Eric Christopher [Fri, 21 May 2010 23:40:03 +0000 (23:40 +0000)]
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
Evan please verify!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408
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Chris Lattner [Fri, 21 May 2010 23:16:21 +0000 (23:16 +0000)]
add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404
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Eric Christopher [Fri, 21 May 2010 23:03:53 +0000 (23:03 +0000)]
Expand on comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396
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Kevin Enderby [Fri, 21 May 2010 23:01:38 +0000 (23:01 +0000)]
Added retl for 32-bit x86 and added retq for 64-bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394
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Eric Christopher [Fri, 21 May 2010 22:39:11 +0000 (22:39 +0000)]
Fix comment and whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104392
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Chris Lattner [Fri, 21 May 2010 22:20:54 +0000 (22:20 +0000)]
expand on the llvm ir bitcode dox. Patch by Peter Housel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104391
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Evan Cheng [Fri, 21 May 2010 21:22:19 +0000 (21:22 +0000)]
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385
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Eric Christopher [Fri, 21 May 2010 21:08:52 +0000 (21:08 +0000)]
Fix section attribute name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381
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Bob Wilson [Fri, 21 May 2010 21:05:32 +0000 (21:05 +0000)]
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380
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Evan Cheng [Fri, 21 May 2010 20:53:24 +0000 (20:53 +0000)]
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377
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Jakob Stoklund Olesen [Fri, 21 May 2010 20:02:01 +0000 (20:02 +0000)]
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372
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Devang Patel [Fri, 21 May 2010 18:49:09 +0000 (18:49 +0000)]
Simplify
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338
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Dale Johannesen [Fri, 21 May 2010 18:44:47 +0000 (18:44 +0000)]
Previous commit message should refer to 104308.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337
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Dale Johannesen [Fri, 21 May 2010 18:40:15 +0000 (18:40 +0000)]
Fix two bugs in 104348:
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336
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Nathan Jeffords [Fri, 21 May 2010 18:23:56 +0000 (18:23 +0000)]
added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104334
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Chris Lattner [Fri, 21 May 2010 18:17:54 +0000 (18:17 +0000)]
now that fp reg kill insertion stuff happens as a separate
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333
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Chris Lattner [Fri, 21 May 2010 18:02:42 +0000 (18:02 +0000)]
Use less evil form of switch stmt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104331
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Chris Lattner [Fri, 21 May 2010 18:01:24 +0000 (18:01 +0000)]
use continue to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104330
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Chris Lattner [Fri, 21 May 2010 17:57:03 +0000 (17:57 +0000)]
pull a nested loop of this pass out to its own function,
eliminating the gymnastics around the ContainsFPCode var.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328
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Chris Lattner [Fri, 21 May 2010 17:49:07 +0000 (17:49 +0000)]
modernize this pass a bit, fit in 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326
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Chris Lattner [Fri, 21 May 2010 17:47:50 +0000 (17:47 +0000)]
constify accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325
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Jakob Stoklund Olesen [Fri, 21 May 2010 17:36:32 +0000 (17:36 +0000)]
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323
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Jakob Stoklund Olesen [Fri, 21 May 2010 16:42:30 +0000 (16:42 +0000)]
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322
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Jakob Stoklund Olesen [Fri, 21 May 2010 16:36:13 +0000 (16:36 +0000)]
Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321
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Jakob Stoklund Olesen [Fri, 21 May 2010 16:32:16 +0000 (16:32 +0000)]
If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320
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Matt Fleming [Fri, 21 May 2010 12:54:43 +0000 (12:54 +0000)]
Currently, createMachOStreamer() is invoked directly in llvm-mc which
isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318
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Matt Fleming [Fri, 21 May 2010 11:39:07 +0000 (11:39 +0000)]
Split out the x86_32 an x86_64 ELF backends as they handle ELF
differently. This will make adding ELF support easier in the long run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317
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Matt Fleming [Fri, 21 May 2010 11:36:59 +0000 (11:36 +0000)]
Add support for parsing the ELF .type assembler directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316
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Lang Hames [Fri, 21 May 2010 03:04:04 +0000 (03:04 +0000)]
Removed scaleNumbering method declaration from LiveInterval (not defined, not used).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104311
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Dale Johannesen [Fri, 21 May 2010 00:52:33 +0000 (00:52 +0000)]
Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308
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Evan Cheng [Fri, 21 May 2010 00:43:17 +0000 (00:43 +0000)]
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307
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Evan Cheng [Fri, 21 May 2010 00:42:32 +0000 (00:42 +0000)]
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306
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Daniel Dunbar [Fri, 21 May 2010 00:27:55 +0000 (00:27 +0000)]
Remove dead option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104303
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Devang Patel [Fri, 21 May 2010 00:10:20 +0000 (00:10 +0000)]
Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302
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Daniel Dunbar [Thu, 20 May 2010 23:50:19 +0000 (23:50 +0000)]
Fix __crashreport_info__ declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104300
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Evan Cheng [Thu, 20 May 2010 23:26:43 +0000 (23:26 +0000)]
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293
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Dan Gohman [Thu, 20 May 2010 22:46:54 +0000 (22:46 +0000)]
DominatorTree.getNode can return null for unreachable blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104290
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Dan Gohman [Thu, 20 May 2010 22:25:20 +0000 (22:25 +0000)]
Minor code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104287
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Mikhail Glushenkov [Thu, 20 May 2010 21:11:37 +0000 (21:11 +0000)]
Print a space after the colon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104279
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Dan Gohman [Thu, 20 May 2010 20:59:23 +0000 (20:59 +0000)]
Make Solve check its own post-condition, to reduce clutter in the
top-level LSRInstance logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278
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Dan Gohman [Thu, 20 May 2010 20:52:00 +0000 (20:52 +0000)]
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276
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Daniel Dunbar [Thu, 20 May 2010 20:36:29 +0000 (20:36 +0000)]
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275
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Devang Patel [Thu, 20 May 2010 20:35:24 +0000 (20:35 +0000)]
Rename variable. add comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274
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Dan Gohman [Thu, 20 May 2010 20:33:18 +0000 (20:33 +0000)]
More code cleanups. Use iterators instead of indices when indices
aren't needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273
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Daniel Dunbar [Thu, 20 May 2010 20:20:39 +0000 (20:20 +0000)]
X86: Model i64i32imm properly, as a subclass of all immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272
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Daniel Dunbar [Thu, 20 May 2010 20:20:35 +0000 (20:20 +0000)]
X86: Fix immediate type of FOO64i32 operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271
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Daniel Dunbar [Thu, 20 May 2010 20:20:32 +0000 (20:20 +0000)]
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270
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Dan Gohman [Thu, 20 May 2010 20:05:31 +0000 (20:05 +0000)]
Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set
Changed directly instead of using a return value.
Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104269
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Dan Gohman [Thu, 20 May 2010 20:00:41 +0000 (20:00 +0000)]
Add some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104268
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Dan Gohman [Thu, 20 May 2010 20:00:25 +0000 (20:00 +0000)]
Simplify this code. Don't do a DomTreeNode lookup for each visited block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104267
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Devang Patel [Thu, 20 May 2010 19:57:06 +0000 (19:57 +0000)]
Refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265
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Matt Fleming [Thu, 20 May 2010 19:45:09 +0000 (19:45 +0000)]
Grammar fix. This is a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104264
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Dan Gohman [Thu, 20 May 2010 19:44:23 +0000 (19:44 +0000)]
Minor code cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104263
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Dan Gohman [Thu, 20 May 2010 19:26:52 +0000 (19:26 +0000)]
When canonicalizing icmp operand order to put the loop invariant
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.
Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262
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Mikhail Glushenkov [Thu, 20 May 2010 19:23:47 +0000 (19:23 +0000)]
llvmc: Make segfault detection work on Win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104261
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Dan Gohman [Thu, 20 May 2010 19:16:03 +0000 (19:16 +0000)]
Set Changed to true when canonicalizing ICmp operand order; even though
it isn't a very interesting change, it's a change nonetheless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104260
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Bob Wilson [Thu, 20 May 2010 18:39:53 +0000 (18:39 +0000)]
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
This fixes the remaining issue with pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257
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Jim Grosbach [Thu, 20 May 2010 18:34:01 +0000 (18:34 +0000)]
Remove dbg_value workaround and associated command line option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254
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Dan Gohman [Thu, 20 May 2010 18:05:01 +0000 (18:05 +0000)]
Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't
have a pattern and it had an invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244
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Dale Johannesen [Thu, 20 May 2010 17:48:26 +0000 (17:48 +0000)]
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems.
7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238
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Devang Patel [Thu, 20 May 2010 16:49:22 +0000 (16:49 +0000)]
Strip llvm.dbg.lv also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104236
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Dan Gohman [Thu, 20 May 2010 16:41:11 +0000 (16:41 +0000)]
Rename a variable to avoid shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104234
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Devang Patel [Thu, 20 May 2010 16:36:41 +0000 (16:36 +0000)]
Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233
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Dan Gohman [Thu, 20 May 2010 16:23:28 +0000 (16:23 +0000)]
Minor code simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104232
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