Reinstate r146578; it doesn't appear to be the cause of some recent execution-
time regressions.  In general, it is beneficial to compile-time.

Original commit message:
Fix for bug #11429: Wrong behaviour for switches. Small improvement for code
size heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147175 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.

The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some bogus comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8

fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147159 91177308-0d34-0410-b5e6-96231b3b80d8

ARM pre-UAL aliases. fcmp[sd].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8

Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting
it. It does need some some tests...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembler should accept shift-by-zero for any shifted-immediate operand.

Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up. Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8

Nuke invalid comment from copy/paste.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8

Give string constants generated by IRBuilder private linkage.

Fixes PR11640.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147144 91177308-0d34-0410-b5e6-96231b3b80d8

Add configure support for kfreebsd and hurd. Patch by Sylvestre Ledru.
Fixes pr11620.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147143 91177308-0d34-0410-b5e6-96231b3b80d8

Make the unreachable probability much much heavier. The previous
probability wouldn't be considered "hot" in some weird loop structures
or other compounding probability patterns. This makes it much harder to
confuse, but isn't really a principled fix. I'd actually like it if we
could model a zero probability, as it would make this much easier to
reason about. Suggestions for how to do this better are welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147142 91177308-0d34-0410-b5e6-96231b3b80d8

Kill the monstrosity that was ELFObjectWriter.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147136 91177308-0d34-0410-b5e6-96231b3b80d8

Misc cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147135 91177308-0d34-0410-b5e6-96231b3b80d8

Fix APInt::rotl and APInt::rotr so that they work correctly.  Found while writing some code that tried to use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147134 91177308-0d34-0410-b5e6-96231b3b80d8

Move the Mips only bits of the ELF writer to lib/Target/Mips.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147133 91177308-0d34-0410-b5e6-96231b3b80d8

Make the virtual methods in ARMELFObjectWriter public.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8

Speculatively revert r146578 to determine if it is the cause of a number of
performance regressions (both execution-time and compile-time) on our
nightly testers.

Original commit message:
Fix for bug #11429: Wrong behaviour for switches. Small improvement for code
size heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147131 91177308-0d34-0410-b5e6-96231b3b80d8

Move the MBlaze ELF writer bits to lib/Target/MBlaze.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147129 91177308-0d34-0410-b5e6-96231b3b80d8

Hoisted some loop invariant smallvector lookups out of a MachineLICM loop

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147127 91177308-0d34-0410-b5e6-96231b3b80d8

Fix cmake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8

Changed MachineLICM to use a worklist list MachineCSE instead of recursion.

Fixes <rdar://problem/10584116>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147125 91177308-0d34-0410-b5e6-96231b3b80d8

Move PPC bits to lib/Target/PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8

Hopefully fix the cmake build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8

Fix name in comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8

Local dynamic TLS model for direct object output. Create the correct TLS MIPS
ELF relocations.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak cmake build after r147115.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8

Move the ARM specific parts of the ELF writer to Target/ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8

getEFlags is const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147114 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147113 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON mnemonic aliase for vrecpeq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8

ARM VFP optional data type on VMOV GPR<-->SPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON optional data type on VSWP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON mnemonic aliases for vzipq and vswpq.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8

Revert patch from 147090. There is not point to make code less readable if we
don't get any serious benefit there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147101 91177308-0d34-0410-b5e6-96231b3b80d8

ARM asm parser should be more lenient w/ .thumb_func directive.

Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a copy+pasto. No testcase, because the symptoms of dereferencing
an invalid iterator aren't reproducible.  rdar://10614085.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147098 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 assembly parsing of 'mov rd, rn, rrx'.

Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8

Fix 80-column violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8

Thumb2 assembly parsing of 'mov(register shifted register)' aliases.

These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8

Continue counting intrinsics as instructions (except when they aren't, such as
debug info) and for being vector operations. Fixes regression from r147037.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147093 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo and spacing, no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147092 91177308-0d34-0410-b5e6-96231b3b80d8

- Change a few operator[] to lookup which is cheaper.
- Add some constantness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147090 91177308-0d34-0410-b5e6-96231b3b80d8

Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147089 91177308-0d34-0410-b5e6-96231b3b80d8

Remove disused STL header include.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147088 91177308-0d34-0410-b5e6-96231b3b80d8

Switch from WriteEFlags to getEFlags in preparation for moving it
to Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147087 91177308-0d34-0410-b5e6-96231b3b80d8

Move common code into an MRI function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON assmebly parsing for VLD2 to all lanes instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8

No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
necessary.  Please chime in if I'm mistaken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a couple of copy-n-paste bugs. Noticed by George Russell!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8

Changes the JSON parser to use the SourceMgr.

Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147063 91177308-0d34-0410-b5e6-96231b3b80d8

Move the X86 specific bits of the ELF writer to the Target/X86 directory.

Other targets will follow shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8

Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8

Add const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147054 91177308-0d34-0410-b5e6-96231b3b80d8

Small refactoring so that RelocNeedsGOT can stay in the target independent
side when the target specific bits are moved to the Target directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147053 91177308-0d34-0410-b5e6-96231b3b80d8

Removes unused field TheError from LLLexer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147049 91177308-0d34-0410-b5e6-96231b3b80d8

Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo in a couple comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8

A call to a function marked 'noinline' is not an inline candidate. The sole
call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147037 91177308-0d34-0410-b5e6-96231b3b80d8

Make some intrinsics safe to speculatively execute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147036 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a couple of copy-n-paste bugs. Noticed by George Russell.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing allows constant expressions for lane indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147027 91177308-0d34-0410-b5e6-96231b3b80d8

ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8

Fix bug in zero-store peephole pattern reported in pr11615.

The patch and test case were originally written by Mans Rullgard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8

Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8

Expand 64-bit CTPOP and CTTZ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8

Expand 64-bit atomic load and store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for r147017.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147018 91177308-0d34-0410-b5e6-96231b3b80d8

Add definition of DSBH (Double Swap Bytes within Halfwords) and
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8

Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.

WSBW is removed since it is not an instruction the current architectures
support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8

64-bit uint-fp conversion nodes are expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8

Enable custom lowering DYNAMIC_STACKALLOC nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8

Set the correct stack pointer register that should be saved or restored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8

Enable and fix a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on
the build bot in some cases.  The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type.  It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext.  We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.

Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is
pretty great that way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147010 91177308-0d34-0410-b5e6-96231b3b80d8

ARM .req register name aliases are case insensitive, just like regnames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8

Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8

Fix indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8

64-bit data directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8

32-to-64-bit sext_inreg pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8

Add 64-bit extload patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8

Add patterns for matching extloads with 64-bit address. The patterns are enabled
only when the target ABI is N64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8

Move comment to appropriate place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8

Add code in MipsDAGToDAGISel for selecting constant +0.0.
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8

Heed spill slot alignment on ARM.

Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8

Revert part of r146995 that was accidentally commmitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996 91177308-0d34-0410-b5e6-96231b3b80d8

32-to-64-bit sign extension pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995 91177308-0d34-0410-b5e6-96231b3b80d8

Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
only when the target ABI is N64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing and encoding for VST2 single-element, double spaced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8

Fix assert condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146987 91177308-0d34-0410-b5e6-96231b3b80d8

Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986 91177308-0d34-0410-b5e6-96231b3b80d8

ARM enable a few more tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8

Add support to add named metadata operand.
Patch by Andrew Wilkins!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146984 91177308-0d34-0410-b5e6-96231b3b80d8

ARM assembly parsing and encoding for VLD2 single-element, double spaced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8

ARM target code clean up. Check for iOS, not Darwin where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8

First steps in ARM AsmParser support for .eabi_attribute and .arch
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8

This is the second fix related to VZEXT_MOVL node.
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8

Begin teaching the X86 target how to efficiently codegen patterns that
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8