Teach ExpandShift how to handle shifts by a constant.  This allows targets
like PowerPC to codegen long shifts in many fewer instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21122 91177308-0d34-0410-b5e6-96231b3b80d8

fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21121 91177308-0d34-0410-b5e6-96231b3b80d8

Fix SingleSource/Regression/C/2005-05-06-LongLongSignedShift.c, we were not
properly sign extending the top of the result of a 64-bit shift right by
a constant > 32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21120 91177308-0d34-0410-b5e6-96231b3b80d8

simplified

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21119 91177308-0d34-0410-b5e6-96231b3b80d8

added first alpha codegen regression test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21117 91177308-0d34-0410-b5e6-96231b3b80d8

Added Nate's div by constant stuff, also scaled operations!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21116 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a namespace issue, reported by Vladimir Merzliakov!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21115 91177308-0d34-0410-b5e6-96231b3b80d8

steal sampo's div-by-constant-power-of-2 stuff
thanks sampo!!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21113 91177308-0d34-0410-b5e6-96231b3b80d8

add fms instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21112 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed version of optimized integer divide is now fixed.  Calculate the
quotient, not the remainder.  Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8

lie a bit and say that r1/r12 (GP/SP) _aren't_ callee-save, as we take
care of this ourselves

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21110 91177308-0d34-0410-b5e6-96231b3b80d8

make sure 'special' registers don't get allocated

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21109 91177308-0d34-0410-b5e6-96231b3b80d8

document these nodes, as they are nonobvious

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21108 91177308-0d34-0410-b5e6-96231b3b80d8

Add (untested) support for MULHS and MULHU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21107 91177308-0d34-0410-b5e6-96231b3b80d8

add signed versions of the extra precision multiplies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21106 91177308-0d34-0410-b5e6-96231b3b80d8

Turn off the div -> mul optimization until it works correctly 100% of the
time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21105 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8

Expand SREM and UREM for targets that claim not to have them, like PowerPC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21103 91177308-0d34-0410-b5e6-96231b3b80d8

Add MULHU and MULHS nodes for the high part of an (un)signed 32x32=64b
multiply.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21102 91177308-0d34-0410-b5e6-96231b3b80d8

added lowerargs support for varargs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21101 91177308-0d34-0410-b5e6-96231b3b80d8

Behold, rlwinm with certain immediate arguments is printed as the much more
readable slwi or srwi (shift left/right word immediate).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21099 91177308-0d34-0410-b5e6-96231b3b80d8

Fix cut & paste errors (32->64), and codegen float->int more optimally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21098 91177308-0d34-0410-b5e6-96231b3b80d8

Updated to use dep analyzer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21097 91177308-0d34-0410-b5e6-96231b3b80d8

Remove 64 bit simple ISel, it never worked correctly
Add initial (buggy) implementation of 64 bit pattern ISel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8

Back out the previous change to SelectBranchCC, since there are cases it
could miscompile.  A correct solution will be found in the near future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21095 91177308-0d34-0410-b5e6-96231b3b80d8

Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
  indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21094 91177308-0d34-0410-b5e6-96231b3b80d8

do not crash when using -debug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21092 91177308-0d34-0410-b5e6-96231b3b80d8

Implement SDIV by power of 2 as srawi/addze rather than load imm, divw

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21091 91177308-0d34-0410-b5e6-96231b3b80d8

Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21090 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for multiply-add, multiply-sub, and their negated versions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8

do not dereference an extra layer of pointers to determine if an external
call can modify a memory location.  This fixes
test/Regression/Analysis/Andersens/modreftest.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21088 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21087 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure that arg regs used by the call instruction are marked as such, so
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8

Remove unnecessary register copy now that regalloc is fixed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to notice that explicit physregs are used in the function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21084 91177308-0d34-0410-b5e6-96231b3b80d8

i1 loads should also be from the low byte of the argument word.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21077 91177308-0d34-0410-b5e6-96231b3b80d8

Fix i64 return, fix CopyFromReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8

fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.

fixes multisource/obsequi (maybe others)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21075 91177308-0d34-0410-b5e6-96231b3b80d8

add implicit use op

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21074 91177308-0d34-0410-b5e6-96231b3b80d8

Handle expanding arguments to ISD::TRUNCATE.  This happens on PowerPC when
you have something like i16 = truncate i64.  This fixes Regression/C/casts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21073 91177308-0d34-0410-b5e6-96231b3b80d8

Fix sign_extend and zero_extend of promoted value types to expanded value
types.  This occurs when casting short to long on PPC for example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21072 91177308-0d34-0410-b5e6-96231b3b80d8

Full varargs support.  All of UnitTests now passes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21070 91177308-0d34-0410-b5e6-96231b3b80d8

Pass the correct value for the chain to the store

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21066 91177308-0d34-0410-b5e6-96231b3b80d8

Fix SHL_PARTS
Start implementation of integer varargs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8

is this simpler?  I think it is simpler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21064 91177308-0d34-0410-b5e6-96231b3b80d8

fix 101 regressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21063 91177308-0d34-0410-b5e6-96231b3b80d8

a wise man once said:

"!!!!!!!! IF YOU CHANGE SPACES TO TABS, YOU WILL BE KILLED!!!!!!"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21062 91177308-0d34-0410-b5e6-96231b3b80d8

.bss is no problem here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21061 91177308-0d34-0410-b5e6-96231b3b80d8

Keeping up with the Joneses.
Implement not, nor, nand, and eqv

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21060 91177308-0d34-0410-b5e6-96231b3b80d8

Select optimization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21051 91177308-0d34-0410-b5e6-96231b3b80d8

Try several things.  1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21046 91177308-0d34-0410-b5e6-96231b3b80d8

fix some VC compilation problems, thanks to Jeff C for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21044 91177308-0d34-0410-b5e6-96231b3b80d8

EquivClassGraphs is now in DataStructure.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21042 91177308-0d34-0410-b5e6-96231b3b80d8

merge EquivClassGraphs.h into DataStructure.h with the other DSA pass definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21041 91177308-0d34-0410-b5e6-96231b3b80d8

use a callee_iterator typedef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21038 91177308-0d34-0410-b5e6-96231b3b80d8

add and use a callee_iterator typedef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21037 91177308-0d34-0410-b5e6-96231b3b80d8

Change the ActualCallees callgraph from hash_multimap<Instruction,Function>
to std::set<std::pair<Inst,Func>> to avoid duplicate entries.

This speeds up the CompleteBU pass from 1.99s to .15s on povray and the
eqgraph passes from 1.5s to .16s on the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21031 91177308-0d34-0410-b5e6-96231b3b80d8

Change the ActualCallees callgraph from hash_multimap<Instruction,Function>
to std::set<std::pair<Inst,Func>> to avoid duplicate entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21030 91177308-0d34-0410-b5e6-96231b3b80d8

FNEG/FABS/UNDEF

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21029 91177308-0d34-0410-b5e6-96231b3b80d8

FNEG/FABS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21028 91177308-0d34-0410-b5e6-96231b3b80d8

this has now been fixed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21026 91177308-0d34-0410-b5e6-96231b3b80d8

ia64 asmprinter fixes:
  - turn off assembler's autoalignment
  - set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
    functions have their value wrapped in @fptr(), so that a function
    descriptor will be materialized for that function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21025 91177308-0d34-0410-b5e6-96231b3b80d8

add support for prefix/suffix strings to go around GlobalValue(s)
(which may or be function pointers) in the asmprinter. For the moment,
this changes nothing, except the IA64 backend which can use this to write:

  data8.ua  @fptr(blah__blah__mangled_function_name)

  (by setting FunctionAddrPrefix/Suffix to "@fptr(" / ")")

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21024 91177308-0d34-0410-b5e6-96231b3b80d8

support IDEF, fnegabs (thanks sampo)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21023 91177308-0d34-0410-b5e6-96231b3b80d8

add fnegabs op

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21022 91177308-0d34-0410-b5e6-96231b3b80d8

Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8

don't forget to use the right code generator :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21017 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21016 91177308-0d34-0410-b5e6-96231b3b80d8

add support for FABS and FNEG

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21015 91177308-0d34-0410-b5e6-96231b3b80d8

transform fabs/fabsf calls into FABS nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21014 91177308-0d34-0410-b5e6-96231b3b80d8

Expand fabs into fneg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21013 91177308-0d34-0410-b5e6-96231b3b80d8

add support FNEG and FABS

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8

Turn -0.0 - X -> fneg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21011 91177308-0d34-0410-b5e6-96231b3b80d8

This target doesn't support fabs/fneg yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8

Several changes mixed up here.  First when legalizing a DAG with pcmarker,
dont' regen the whole dag if unneccesary.  Second, fix and ugly bug with
the _PARTS nodes that caused legalize to produce multiples of them.
Finally, implement initial support for FABS and FNEG.  Currently FNEG is
the only one to be trusted though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21009 91177308-0d34-0410-b5e6-96231b3b80d8

print fneg/fabs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21008 91177308-0d34-0410-b5e6-96231b3b80d8

Add two happy new nodes for FABS and FNEG

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21007 91177308-0d34-0410-b5e6-96231b3b80d8

add an fabs instr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21006 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for 64-bit shifts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21005 91177308-0d34-0410-b5e6-96231b3b80d8

fix some bugs in the implementation of SHL_PARTS and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21004 91177308-0d34-0410-b5e6-96231b3b80d8

fix a comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21003 91177308-0d34-0410-b5e6-96231b3b80d8

Turn expanded shift operations into (e.g.) SHL_PARTS if the target supports it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21002 91177308-0d34-0410-b5e6-96231b3b80d8

Print some new nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21001 91177308-0d34-0410-b5e6-96231b3b80d8

add some new nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21000 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug when inserting a libcall into a function with no other calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20999 91177308-0d34-0410-b5e6-96231b3b80d8

new generic testcsae

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20996 91177308-0d34-0410-b5e6-96231b3b80d8

Fix i64 returns
Generate PowerPC 'subfic' instruction when appropriate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a warning about an unhandled switch case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20994 91177308-0d34-0410-b5e6-96231b3b80d8

For Sparc, this xfails.  I don't think sparc has the C99 complex data
type support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20993 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for ISD::UNDEF to the X86 be

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20990 91177308-0d34-0410-b5e6-96231b3b80d8

Add ISD::UNDEF node
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20988 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another PATypeHolder error, contributed by Bill Wendling!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20983 91177308-0d34-0410-b5e6-96231b3b80d8

repair mindless SELECT waste.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20982 91177308-0d34-0410-b5e6-96231b3b80d8

Fix Olden/bh, CR0 was being set in the wrong order
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20981 91177308-0d34-0410-b5e6-96231b3b80d8

Also apply Chris's fix to FP select and SETCC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20979 91177308-0d34-0410-b5e6-96231b3b80d8

new testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20978 91177308-0d34-0410-b5e6-96231b3b80d8

Move the selection of the arms of the select operation up to the conditional
part to make sure we get the side effects and to avoid confusing the CFG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20977 91177308-0d34-0410-b5e6-96231b3b80d8

print the machine CFG in the -print-machineinstrs dump

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20976 91177308-0d34-0410-b5e6-96231b3b80d8

Fix stores to global addresses
Fix calls with no arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20975 91177308-0d34-0410-b5e6-96231b3b80d8

Support indexed loads and stores.  This drops Shootout/matrix time from
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20973 91177308-0d34-0410-b5e6-96231b3b80d8