drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: kick vram functions out into an "engine"

NVC0 will be able to share some of nv50's paths this way.  This also makes
it the card-specific vram code responsible for deciding if a given set
of tile_flags is valid, rather than duplicating the allowed types in
nv50_vram.c and nouveau_gem.c

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: allow gpuobj vinst to be a virtual address when necessary

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: tidy up PCIEGART implementation

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: enable non-contig vram allocations where requested

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: enable 4KiB pages for small vram allocations

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: implement global channel address space on new VM code

As of this commit, it's guaranteed that if an object is in VRAM that its
GPU virtual address will be constant.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: implement BAR1/BAR3 management on top of new VM code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: import new vm code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: implement custom vram mm

This is required on nv50 as we need to be able to have more precise control
over physical VRAM allocations to avoid buffer corruption when using
buffers of mixed memory types.

This removes some nasty overallocation/alignment that we were previously
using to "control" this problem.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Avoid potential race between nouveau_fence_update() and context takedown.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: fix use of drm_mm_node in semaphore object

At some point in the future, this bo won't necessarily be backed by
a drm_mm_node, so use the start/size fields of the ttm_mem_reg instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: wrap calls to ttm_bo_validate()

This will be used later to fixup bo.offset with a buffer's fixed GPU
virtual address.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: no need to zero dma objects, we fill them completely anyway

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: introduce a util function to wait on reg != val

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: implicitly insert non-DMA objects into RAMHT

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: make fifo.create_context() responsible for mapping control regs

The regs belong to PFIFO, they're different for pretty much the same
generations we need different PFIFO control for, and NVC0 is going
to be even more different than the rest.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU.

Sleeping doesn't pay off for very short delays in comparison with the
minimum granularity of schedule_timeout().

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Use WC memory on the AGP GART.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Synchronize with the user channel before GPU object destruction.

There have been reports of PFIFO cache errors during context take down
(fdo bug 31637). They are caused by some GPU objects being taken out
while the channel is still potentially processing commands. Make sure
that all the previous rendering has landed before releasing a GPU
object.

Reported-by: Grzesiek Sójka <pld@pfu.pl>
Reported-by: Patrice Mandin <patmandin@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.

nvxx_graph_isr is already taking care of it. In some cases this
could've made you miss PGRAPH interrupts (e.g. when you were supposed
to get several IRQs of the same kind in a row).

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.

No functional changes, just simplify some code paths a bit.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: fabricate DCB encoder table for iMac G4

In typical Apple fashion there's no standard information about what
encoders are present on this machine, this patch adds a quirk to
provide it.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: tidy up and extend dma object creation interfaces

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: remove some useless GETPARAMs

These have been unused since UMS support was ripped out, so lets remove
them completely.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv84: fix minor issues in PCRYPT implementation

Fix running of destroy_context() when create_context() has never been
called for the channel, and fill in engine's tlb_flush() function pointer.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present instead

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: fix 0x100c90 init for NVAF

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: allocate page for unknown PFB object in nv50_fb.c

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: rework gpu-specific instmem interfaces

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: simplify gpuobj suspend/resume

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: rework PGPIO IRQ handling and hotplug detection

Allows callers to install their own handlers for when a GPIO line
changes state (such as for hotplug detect).

This also fixes a bug where we weren't acknowledging the GPIO IRQ
until after the bottom half had run, causing a severe IRQ storm
in some cases.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv04-nv40: unregister irq handler on destroy

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c files

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: move PFIFO ISR into nv04_fifo.c

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv04-nv40: register vblank isr

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: move bitfield/enum helpers to nouveau_util.c

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: use register/unregister functionality for PDISPLAY ISR

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: move GPIO ISR to nv50_gpio.c

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv84: move PCRYPT ISR out of nouveau_irq.c

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: allow irq handlers to be installed by engine-specific code

Lets start to clean up this mess!

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: 0x50c0 apparently works on NVA3+ too, so lets allow it

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: fix compute object class

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Fix sleep while atomic in nouveau_bo_fence().

Reported-by: Pekka Paalanen <pq@iki.fi>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv20: Add Z compression support.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Xavier Chantry <chantry.xavier@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Rework tile region handling.

The point is to share more code between the PFB/PGRAPH tile region
hooks, and give the hardware specific functions a chance to allocate
per-region resources.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Add a separate class for the kernel channel mutex.

nouveau_bo_move_m2mf() needs to lock the kernel channel, and it may be
called from the pushbuf IOCTL with an user channel already locked. Use
a separate subclass for the kernel channel mutex because this is
legitimate mutex nesting.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: Keep track of the head a channel is vsync'ing to.

In a multihead setup vblank interrupts may end up enabled in both
heads. In that case we want to ignore the vblank interrupts coming
from the wrong CRTC to avoid tearing and unbalanced calls to
drm_vblank_get/put (fdo bug 31074).

Reported-by: Felix Leimbach <felix.leimbach@gmx.net>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Call drm_vblank_pre/post_modeset() around mode setting.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Implement the pageflip ioctl.

nv0x-nv4x should be mostly fine, nv50 doesn't work yet.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Implement the vblank DRM hooks.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv04: Make CRTC base changes effective in the next hsync.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: fix annoying nouveau_fence type issue

nouveau_fence_* functions are not type safe, which could lead to bugs.
Additionally every use of nouveau_fence_unref had to cast struct
nouveau_fence to void **.
Fix it by renaming old functions and creating static inline functions with
new prototypes. We still need old functions, because we pass function
pointers to ttm.
As we are wrapping functions, drop unused "void *arg" parameter where possible.

Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: regression fix, point NVAA/NVAC at correct PM functions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: add support for MSI

Only supported on NV50+ so far, and disabled by default currently.  The
module parameter "msi=1" will enable it.

There's a kernel bug which will cause this to fail if the module (or the
NVIDIA binary driver) has ever been loaded before loading nouveau with
MSI enabled.  As such, this is only safe to enable if you have nouveau
load on boot, and don't wish to ever reload it.

The workaround is to "echo 0 > /sys/bus/pci/devices/<device>/enable"
until the enable count reads 0.  Then you should be able to load nouveau
with MSI enabled.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv10: fix thinko and let nv17 do 3d again :)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: fix evo instmem alignment

Not an issue right now, we're forced to 64k size/alignment by the BO
allocator anyway.  This won't be the case soon.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: improve evo error handler when more than just channel 0 active

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: rework evo init to match nvidia more closely

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: initial work to allow multiple evo channels

This doesn't work yet for unknown reasons.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: move evo handling to nv50_evo.c

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: clearer separation of the stages of evo init

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: create graph and crypt contexts on demand

This really needs cleaning up somehow, and probably investigate what's
needed to do this on earlier generations.  NVIDIA do something similar
there too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: remove excessive alignment of graph/crypt contexts

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv84: add support for the PCRYPT engine

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: only expose the object classes that are supported by the chipset

We previously added all the available classes for the entire generation,
even though the objects wouldn't work on the hardware.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: use object class structs more extensively

The structs themselves, as well as the non-sw object creation function are
probably very misnamed now.  That's a problem for later :)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: store engine type in gpuobj class structs

We will eventually want to address hw engines other than PGRAPH.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: pass gpuobj alignment request down into backing allocator

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv40: Ignore sync-to-vblank active when waiting for idle.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Take fence spinlock in nouveau_fence_channel_fini().

Without it there's a potential race with nouveau_fence_update().

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Avoid race in the interchannel sync code.

It needs a "strong" channel reference because it actually writes to
the channel pushbuf, otherwise the corresponding FIFO context could
get kicked off in the middle of nouveau_fence_sync().

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Make fences take a weak channel reference.

Fences didn't increment the channel reference count, and the fenced
channel could go away at any time. Fixes a potential race in
nouveau_fence_update().

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Implement weak channel references.

nouveau_channel_ref() takes a "weak" channel reference that doesn't
prevent the hardware channel resources from being released, it just
keeps the channel data structure alive.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Fix lock unbalance on card take down.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Add unlocked variants of nouveau_channel_get/put.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Fix race condition in channel refcount handling.

nouveau_channel_put() can be executed after the 'refcount == 0' check
in nouveau_channel_get() and before the channel reference count is
incremented. In that case CPU0 will take the context down while CPU1
thinks it owns the channel and 'refcount == 1'.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Refactor context destruction to avoid a lock ordering issue.

The destroy_context() engine hooks call gpuobj management functions to
release the channel resources, these functions use HARDIRQ-unsafe locks
whereas destroy_context() is called with the HARDIRQ-safe
context_switch_lock held, that's a lock ordering violation.

Push the engine-specific channel destruction logic into destroy_context()
and let the hardware-specific code lock and unlock when it's actually
needed. Change the engine destruction order to avoid a race in the small
gap between pgraph and pfifo context uninitialization.

Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Use lazy fence waits when doing software interchannel sync.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: Leave BO eviction synchronization for later.

The pushbuf ioctl syncs after validation, no need for this anymore.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nv50: remove some unnecessary PDISPLAY init

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: fallback to sw fbcon if we can't get mutex immediately

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: hook up acpi power supply change tracking

Not used at all yet, but lets hook it up now anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: return error from nouveau_ramht_remove() if not found

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: use interruptible waits during pushbuf validation

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: fix thinko in channel locking in semaphore path

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: remove cpu_writers lock

No other driver uses this, and userspace should be responsible for handling
locking between them if they share BOs.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: switch to unlocked ioctls

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: add more fine-grained locking to channel list + structures

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: add per-channel mutex, use to lock access to drm's channel

This fixes a race condition between fbcon acceleration and TTM buffer
moves.  To reproduce:

- start X
- switch to vt and "while (true); do dmesg; done"
- switch to another vt and "sleep 2 && cat /path/to/debugfs/dri/0/evict_vram"
- switch back to vt running dmesg

We don't make use of this on any other channel yet, they're currently
protected by drm_global_mutex.  This will change in the near future.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: disallow fbcon accel if running in interrupt context

A future commit will add locking to the DRM's channel, and there's numerous
problems that come up if we allow printk from an interrupt context to be
accelerated.  It seems saner to just disallow it completely.

As a nice side-effect, all the "to accel or not to accel" logic gets moved
out of the chipset-specific code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drm/nouveau: tidy fifo swmthd handler a little

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Merge branch 'drm-radeon-fusion' of ../drm-radeon-next into drm-core-next

* 'drm-radeon-fusion' of ../drm-radeon-next:
  drm/radeon/kms: add Ontario APU ucode loading support
  drm/radeon/kms: add Ontario Fusion APU pci ids
  drm/radeon/kms: enable MSIs on fusion APUs
  drm/radeon/kms: add power table parsing support for Ontario fusion APUs
  drm/radeon/kms: refactor atombios power state fetching
  drm/radeon/kms: add bo blit support for Ontario fusion APUs
  drm/radeon/kms: add thermal sensor support for fusion APUs
  drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs
  drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs
  drm/radeon/kms: evergreen.c updates for fusion
  drm/radeon/kms: MC setup changes for fusion APUs
  drm/radeon/kms: move r7xx/evergreen to its own vram_gtt setup function
  drm/radeon/kms: add support for ss overrides on Fusion APUs
  drm/radeon/kms: Add support for external encoders on fusion APUs
  drm/radeon/kms: atom changes for DCE4.1 devices
  drm/radeon/kms: add new family id for AMD Ontario APUs
  drm/radeon/kms: upstream power table updates
  drm/radeon/kms: upstream atombios.h updates
  drm/radeon/kms: upstream ObjectID.h updates
  drm/radeon/kms: setup mc chremap properly on r7xx/evergreen

Merge branch 'drm-radeon-next' of ../drm-radeon-next into drm-core-next

* 'drm-radeon-next' of ../drm-radeon-next:
  drm/radeon/kms: improve pflip precision on r1xx-r4xx
  drm/kms/radeon: Use high precision timestamps for pageflip completion events.
  drm/kms/radeon: Reorder vblank and pageflip interrupt handling.
  drm/radeon/kms: add pageflip ioctl support (v3)
  drm/kms/radeon: Add support for precise vblank timestamping.

Merge branch 'drm-ttm-next' into drm-core-next

* drm-ttm-next:
  drm/radeon: Use the ttm execbuf utilities
  drm/ttm: Fix up io_mem_reserve / io_mem_free calling
  drm/ttm/vmwgfx: Have TTM manage the validation sequence.
  drm/ttm: Improved fencing of buffer object lists
  drm/ttm/radeon/nouveau: Kill the bo lock in favour of a bo device fence_lock
  drm/ttm: Don't deadlock on recursive multi-bo reservations
  drm/ttm: Optimize ttm_eu_backoff_reservation
  drm/ttm: Use kref_sub instead of repeatedly calling kref_put
  kref: Add a kref_sub function
  drm/ttm: Add a bo list reserve fastpath (v2)

drm/radeon/kms: improve pflip precision on r1xx-r4xx

The update pending bit has a separate enable bit.

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drm/radeon/kms: add Ontario APU ucode loading support

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drm/radeon/kms: add Ontario Fusion APU pci ids

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drm/radeon/kms: enable MSIs on fusion APUs

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drm/radeon/kms: add power table parsing support for Ontario fusion APUs

The vbios power tables on my inagua board seem a bit funky...

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>