Arnold Schwaighofer [Fri, 5 Jul 2013 18:28:39 +0000 (18:28 +0000)]
ARM: Fix incorrect pack pattern
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them
in the bottom half of "x". An arithmetic and logic shift are only equivalent in
this context if the shift amount is 16. We would be shifting in ones into the
bottom 16bits instead of zeros if "y" is negative.
radar://
14338767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712
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Sylvestre Ledru [Fri, 5 Jul 2013 15:58:12 +0000 (15:58 +0000)]
Remove a useless declarations (found by scan-build)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185709
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Richard Sandiford [Fri, 5 Jul 2013 14:38:48 +0000 (14:38 +0000)]
[SystemZ] Remove no-op MVCs
The stack coloring pass has code to delete stores and loads that become
trivially dead after coloring. Extend it to cope with single instructions
that copy from one frame index to another.
The testcase happens to show an example of this kicking in at the moment.
It did occur in Real Code too though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185705
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Richard Sandiford [Fri, 5 Jul 2013 14:31:24 +0000 (14:31 +0000)]
[SystemZ] Remove redundant frame MMOs
This fixes foldMemoryOperandImpl() so that it doesn't create duplicated
frame MMOs. I hadn't realized when writing r185434 that it was the caller's
responsibility to add these.
No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185704
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Richard Sandiford [Fri, 5 Jul 2013 14:24:47 +0000 (14:24 +0000)]
Fix double renaming bug in stack coloring pass
The stack coloring pass renumbered frame indexes with a loop of the form:
for each frame index FI
for each instruction I that uses FI
for each use of FI in I
rename FI to FI'
This caused problems if an instruction used two frame indexes F0 and F1
and if F0 was renamed to F1 and F1 to F2. The first time we visited the
instruction we changed F0 to F1, then we changed both F1s to F2.
In other words, the problem was that SSRefs recorded which instructions
used an FI, but not which MachineOperands and MachineMemOperands within
that instruction used it.
This is easily fixed for MachineOperands by walking the instructions
once and processing each operand in turn. There's already a loop to
do that for dead store elimination, so it seemed more efficient to
fuse the two at the block level.
MachineMemOperands are more tricky because they can be shared between
instructions. The patch handles them by making SSRefs an array of
MachineMemOperands rather than an array of MachineInstrs. We might end
up processing the same MachineMemOperand twice, but that's OK because
we always know from the SSRefs index what the original frame index was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185703
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Richard Sandiford [Fri, 5 Jul 2013 14:02:01 +0000 (14:02 +0000)]
[SystemZ] Enable the use of MVC for frame-to-frame spills
...now that the problem that prompted the restriction has been fixed.
The original spill-02.py was a compromise because at the time I couldn't
find an example that actually failed without the two scavenging slots.
The version included here did.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185701
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Ulrich Weigand [Fri, 5 Jul 2013 13:49:46 +0000 (13:49 +0000)]
[PowerPC] Add some special @got@tprel fixup cases
When a target@got@tprel or target@got@tprel@l symbol variant is used in
a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail,
since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO
relocation types do not exist.
However, since such symbol variants resolve to GOT offsets which are
always 4-aligned, we can simply instead use the _DS variants of the
relocation types, which *do* exist.
The same applies for the @got@dtprel variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700
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Richard Sandiford [Fri, 5 Jul 2013 13:11:52 +0000 (13:11 +0000)]
[SystemZ] Allocate a second register scavenging slot
This is another prerequisite for frame-to-frame MVC copies.
I'll commit the patch that makes use of the slot separately.
The downside of trying to test many corner cases with each of the
available addressing modes is that a fair few tests need to account
for the new frame layout. I do still think it's useful to have all
these tests though, since it's something that wouldn't get much coverage
otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185698
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Rafael Espindola [Fri, 5 Jul 2013 13:03:07 +0000 (13:03 +0000)]
Don't create an archive if, for example, we are asked to print the index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185697
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Richard Sandiford [Fri, 5 Jul 2013 12:55:00 +0000 (12:55 +0000)]
[SystemZ] Clean up register scavenging code
SystemZ wants normal register scavenging slots, as close to the stack or
frame pointer as possible. The only reason it was using custom code was
because PrologEpilogInserter assumed an x86-like layout, where the frame
pointer is at the opposite end of the frame from the stack pointer.
This meant that when frame pointer elimination was disabled,
the slots ended up being as close as possible to the incoming
stack pointer, which is the opposite of what we want on SystemZ.
This patch adds a new knob to say which layout is used and converts
SystemZ to use target-independent scavenging slots. It's one of the pieces
needed to support frame-to-frame MVCs, where two slots might be required.
The ABI requires us to allocate 160 bytes for calls, so one approach
would be to use that area as temporary spill space instead. It would need
some surgery to make sure that the slot isn't live across a call though.
I stuck to the "isFPCloseToIncomingSP - ..." style comment on the
"do what the surrounding code does" principle. The FP case is already
covered by several Systemz/frame-* tests, which fail without the
PrologueEpilogueInserter change, so no new ones are needed.
No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185696
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Rafael Espindola [Fri, 5 Jul 2013 12:44:49 +0000 (12:44 +0000)]
Use simpler version of exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185695
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Ulrich Weigand [Fri, 5 Jul 2013 12:33:03 +0000 (12:33 +0000)]
[PowerPC] Make test case buildable with GNU as
The ppc64-fixups.s test currently fails to build with GNU as, since it
does not support plain symbols as arguments to li/lis. Rewrite the test
for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead.
Allowing the test case to be built with both LLVM and GNU as makes it
easier to spot unwanted difference in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694
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Ulrich Weigand [Fri, 5 Jul 2013 12:22:36 +0000 (12:22 +0000)]
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692
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Rafael Espindola [Fri, 5 Jul 2013 12:12:43 +0000 (12:12 +0000)]
Remove NoOperation.
parseCommandLine prints and error and exists if no operation is specified, so
it never returns NoOperation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185691
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Benjamin Kramer [Fri, 5 Jul 2013 10:20:57 +0000 (10:20 +0000)]
Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185689
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Joey Gouly [Fri, 5 Jul 2013 10:19:40 +0000 (10:19 +0000)]
PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.
In the SelectionDAG immediate operands to inline asm are constructed as
two separate operands. The first is a constant of value InlineAsm::Kind_Imm
and the second is a constant with the value of the immediate.
In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we
should skip over the next operand too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688
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Rafael Espindola [Fri, 5 Jul 2013 04:19:32 +0000 (04:19 +0000)]
Don't treat bitcode files specially in llvm-ar.
We really want bitcode files to behave as regular object files in archives, so
we don't need to track that a member is bitcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185681
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Rafael Espindola [Fri, 5 Jul 2013 03:35:15 +0000 (03:35 +0000)]
Use the raw member names in Archive::Archive.
This a bit more efficient and avoids having a function that uses the string
table being called by a function that searches for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185680
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Rafael Espindola [Fri, 5 Jul 2013 02:50:03 +0000 (02:50 +0000)]
Add a --crash option to not.
Now the two possible uses of not are
* not cmd
Will return true if cmd doesn't crash and returns false.
* not --crash cmd
Will return true if cmd crashes.
It will be used/tested in a followup commit for the clang crash recovery
testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185678
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David Majnemer [Fri, 5 Jul 2013 00:31:17 +0000 (00:31 +0000)]
InstCombine: (icmp eq B, 0) | (icmp ult A, B) -> (icmp ule A, B-1)
This transform allows us to turn IR that looks like:
%1 = icmp eq i64 %b, 0
%2 = icmp ult i64 %a, %b
%3 = or i1 %1, %2
ret i1 %3
into:
%0 = add i64 %b, -1
%1 = icmp uge i64 %0, %a
ret i1 %1
which means we go from lowering:
cmpq %rsi, %rdi
setb %cl
testq %rsi, %rsi
sete %al
orb %cl, %al
ret
to lowering:
decq %rsi
cmpq %rdi, %rsi
setae %al
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185677
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Ahmed Bougacha [Thu, 4 Jul 2013 23:20:12 +0000 (23:20 +0000)]
Remove use of asymmetric std::lower_bound comparator.
VS 2008 doesn't like it when in debug mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185676
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David Blaikie [Thu, 4 Jul 2013 23:15:18 +0000 (23:15 +0000)]
DebugInfo: Consider global variables without locations to be valid
We were being a bit too aggresive here in classifying global variables
with no global reference or constant value to be invalid - this would
cause LLVM to not emit the DWARF description of the global variable if
it had been optimized away, which isn't helpful for users who might
benefit from the global variable's description even if there's no
location information.
This also fixes a crasher issue here that I was unable to reduce a test
case for - involving a using decl (& subsequent
DW_TAG_imported_declaration ) of such a global variable that, once
optimized away, would crash when an attempt to emit the imported
declaration was made.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185675
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Rafael Espindola [Thu, 4 Jul 2013 22:15:33 +0000 (22:15 +0000)]
Use a OwningPtr instead of a manual delete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185673
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Nico Rieck [Thu, 4 Jul 2013 21:37:26 +0000 (21:37 +0000)]
Initialize object file info before output streamer
r179494 switched to using the object file info to retrieve the default text
section for some MC streamers. It is possible that initializing an MC
streamer can request sections before the object file info is initialized
when the AutoInitSections flag is set on the streamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185670
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Nico Rieck [Thu, 4 Jul 2013 21:32:07 +0000 (21:32 +0000)]
MC: Add .section directive to COFF
Supports GAS flags "abdnrswxy". No support for alignment or subsections.
Fixes PR16366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669
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David Majnemer [Thu, 4 Jul 2013 21:17:49 +0000 (21:17 +0000)]
InstCombine: Reimplementation of visitUDivOperand
This transform was originally added in r185257 but later removed in
r185415. The original transform would create instructions speculatively
and then discard them if the speculation was proved incorrect. This has
been replaced with a scheme that splits the transform into two parts:
preflight and fold. While we preflight, we build up fold actions that
inform the folding stage on how to act.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185667
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Rafael Espindola [Thu, 4 Jul 2013 19:40:23 +0000 (19:40 +0000)]
Add support for archives with no symbol table or string table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185664
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Rafael Espindola [Thu, 4 Jul 2013 19:20:00 +0000 (19:20 +0000)]
Fix leak. Should bring back the valgrind bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185663
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Ulrich Weigand [Thu, 4 Jul 2013 18:28:46 +0000 (18:28 +0000)]
[PowerPC] Implement writeNopData
This implements a proper PPCAsmBackend::writeNopData routine
that actually writes PowerPC nop instructions.
This fixes the last remaining difference in object file output
(text section) between the integrated assembler and GNU as
that I've seen anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662
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Rafael Espindola [Thu, 4 Jul 2013 17:21:01 +0000 (17:21 +0000)]
Add 'not' in front of a command that is expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659
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Aaron Ballman [Thu, 4 Jul 2013 17:05:21 +0000 (17:05 +0000)]
Changing long to int for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185656
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Joey Gouly [Thu, 4 Jul 2013 15:58:38 +0000 (15:58 +0000)]
Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185651
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Joey Gouly [Thu, 4 Jul 2013 14:57:20 +0000 (14:57 +0000)]
Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.
This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642
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Ulrich Weigand [Thu, 4 Jul 2013 14:40:12 +0000 (14:40 +0000)]
[PowerPC] Add all trap mnemonics
This adds support for all basic and extended variants
of the trap instructions to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638
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Ulrich Weigand [Thu, 4 Jul 2013 14:24:00 +0000 (14:24 +0000)]
[PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and
condition register fields via expressions using the symbols
defined by the PowerISA, like "4*cr2+eq".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633
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Benjamin Kramer [Thu, 4 Jul 2013 14:22:02 +0000 (14:22 +0000)]
SimplifyCFG: Teach switch generation some patterns that instcombine forms.
This allows us to create switches even if instcombine has munged two of the
incombing compares into one and some bit twiddling. This was motivated by enum
compares that are common in clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632
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Aaron Ballman [Thu, 4 Jul 2013 14:12:25 +0000 (14:12 +0000)]
Supporting ssize_t on WIN64 with its proper size. Patch thanks to David Cournapeau!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185627
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 13:54:20 +0000 (13:54 +0000)]
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625
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Joey Gouly [Thu, 4 Jul 2013 10:04:08 +0000 (10:04 +0000)]
Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 04:53:49 +0000 (04:53 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185618
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 04:53:45 +0000 (04:53 +0000)]
Simplify landing pad lowering.
Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be scheduled at the top of the
basic block.
This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.
This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.
A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185617
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 04:32:39 +0000 (04:32 +0000)]
FastISel can only apend to basic blocks.
Compute the insertion point from the end of the basic block instead of
skipping labels from the front.
This caused failures in landing pads when live-in copies where inserted
before instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185616
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 04:32:35 +0000 (04:32 +0000)]
Live-in copies go *after* EH_LABELs.
This will soon be tested by exception handling working at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185615
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Nick Lewycky [Thu, 4 Jul 2013 03:51:53 +0000 (03:51 +0000)]
Tabs to spaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185612
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Craig Topper [Thu, 4 Jul 2013 01:43:17 +0000 (01:43 +0000)]
Add a space between closing template '>' to unbreak build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185607
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Craig Topper [Thu, 4 Jul 2013 01:31:24 +0000 (01:31 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185606
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Eric Christopher [Thu, 4 Jul 2013 01:10:38 +0000 (01:10 +0000)]
Reapply r185601 with a fix for the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185605
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Eric Christopher [Thu, 4 Jul 2013 00:51:26 +0000 (00:51 +0000)]
Temporarily revert 185601 as it caused cmake build regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185603
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Eric Christopher [Thu, 4 Jul 2013 00:47:09 +0000 (00:47 +0000)]
Add support for futimens for platforms that don't support futimes.
Patch by pashev.igor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185601
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Jakob Stoklund Olesen [Thu, 4 Jul 2013 00:26:30 +0000 (00:26 +0000)]
Revert r185595-185596 which broke buildbots.
Revert "Simplify landing pad lowering."
Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600
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Jakob Stoklund Olesen [Wed, 3 Jul 2013 23:56:31 +0000 (23:56 +0000)]
Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.
These exception-related opcodes are not used any longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596
91177308-0d34-0410-b5e6-
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Jakob Stoklund Olesen [Wed, 3 Jul 2013 23:56:24 +0000 (23:56 +0000)]
Simplify landing pad lowering.
Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering
landing pad arguments. These nodes were previously legalized into
CopyFromReg nodes, but that never worked properly because the
CopyFromReg node weren't guaranteed to be scheduled at the top of the
basic block.
This meant the exception pointer and selector registers could be
clobbered before being copied to a virtual register.
This patch copies the two physical registers to virtual registers at
the beginning of the basic block, and lowers the landingpad instruction
directly to two CopyFromReg nodes reading the *virtual* registers. This
is safe because virtual registers don't get clobbered.
A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185595
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Jakob Stoklund Olesen [Wed, 3 Jul 2013 23:56:20 +0000 (23:56 +0000)]
Add MachineBasicBlock::addLiveIn().
This function adds a live-in physical register to an MBB and ensures
that it is copied to a virtual register immediately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185594
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Stephen Lin [Wed, 3 Jul 2013 23:39:13 +0000 (23:39 +0000)]
Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for the GHC calling convention.
This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185592
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Eric Christopher [Wed, 3 Jul 2013 22:40:21 +0000 (22:40 +0000)]
Hoist all of the Entry.getLoc() calls int a single variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185589
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Eric Christopher [Wed, 3 Jul 2013 22:40:18 +0000 (22:40 +0000)]
Make DotDebugLocEntry a class, reorder the members along with comments
for them and update all uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185588
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Quentin Colombet [Wed, 3 Jul 2013 21:42:57 +0000 (21:42 +0000)]
[ARM] Improve the instruction selection of vector loads.
In the ARM back-end, build_vector nodes are lowered to a target specific
build_vector that uses floating point type.
This works well, unless the inserted bitcasts survive until instruction
selection. In that case, they incur moves between integer unit and floating
point unit that may result in inefficient code.
In other words, this conversion may introduce artificial dependencies when the
code leading to the build vector cannot be completed with a floating point type.
In particular, this happens when loads are not aligned.
Before this patch, in that case, the compiler generates general purpose loads
and creates the floating point vector from them, instead of directly using the
vector unit.
The patch uses a vector friendly sequence of code when the inserted bitcasts to
floating point survived DAGCombine.
This is done by a target specific DAGCombine that changes the target specific
build_vector into a sequence of insert_vector_elt that get rid of the bitcasts.
<rdar://problem/
14170854>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587
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Eric Christopher [Wed, 3 Jul 2013 21:37:03 +0000 (21:37 +0000)]
Elaborate on comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185586
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Eric Christopher [Wed, 3 Jul 2013 21:23:59 +0000 (21:23 +0000)]
Add names to the header file since they help in documenting the API
(and for consistency).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185585
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Bill Schmidt [Wed, 3 Jul 2013 21:03:35 +0000 (21:03 +0000)]
[PowerPC] FreeBSD does not require f128 in its data layout string.
Long double is 64 bits on FreeBSD PPC, so the f128 entry is superfluous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185583
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Renato Golin [Wed, 3 Jul 2013 20:56:33 +0000 (20:56 +0000)]
Add platform specific tests doc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185581
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Tilmann Scheller [Wed, 3 Jul 2013 20:38:01 +0000 (20:38 +0000)]
ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying certain Thumb2 add immediate T3 encodings.
Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding.
The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process.
This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly.
Fixes <rdar://problem/
14224440>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575
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Eric Christopher [Wed, 3 Jul 2013 20:36:36 +0000 (20:36 +0000)]
Move typedefs inside the class that they belong to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185573
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Chad Rosier [Wed, 3 Jul 2013 18:38:08 +0000 (18:38 +0000)]
Use an RWMutex instead of a Mutex in PassRegistry.
Patch by Alex Crichton <alex@crichton.co>. Approved by Chris Lattner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185566
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Ulrich Weigand [Wed, 3 Jul 2013 18:29:47 +0000 (18:29 +0000)]
[PowerPC] Support lmw/stmw in the asm parser
This adds support for the load/store multiple instructions,
currently used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564
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Ulrich Weigand [Wed, 3 Jul 2013 17:59:07 +0000 (17:59 +0000)]
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561
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Ulrich Weigand [Wed, 3 Jul 2013 17:05:42 +0000 (17:05 +0000)]
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556
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Rafael Espindola [Wed, 3 Jul 2013 16:41:29 +0000 (16:41 +0000)]
Prefix failing commands with not to make clear they are expected to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554
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Rafael Espindola [Wed, 3 Jul 2013 16:35:26 +0000 (16:35 +0000)]
Remove another old test.
It was only passing because 'grep andpd' was not finding any andpd, but
we don't fail if part of a pipe fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185552
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Rafael Espindola [Wed, 3 Jul 2013 16:30:01 +0000 (16:30 +0000)]
Remove test for the old EH system. It doesn't parse anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185551
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Rafael Espindola [Wed, 3 Jul 2013 16:27:55 +0000 (16:27 +0000)]
Fix test: It was missing run lines and llvm-dis has no -disable-verify option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185550
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Rafael Espindola [Wed, 3 Jul 2013 15:57:14 +0000 (15:57 +0000)]
Add support for gnu archives with a string table and no symtab.
While there, use early returns to reduce nesting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185547
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Rafael Espindola [Wed, 3 Jul 2013 15:46:03 +0000 (15:46 +0000)]
Make llvm-nm return 1 on error.
This is a small compatibility improvement with gnu nm and makes llvm-nm more
useful as a testing tool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185546
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Ulrich Weigand [Wed, 3 Jul 2013 15:13:30 +0000 (15:13 +0000)]
[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC
The subroutine getCRIdxForSetCC has a parameter "Other" and comment:
If this returns with Other != -1, then the returned comparison
is an or of two simpler comparisons.
However for at least the last five years this routine has never
returned a value of Other != -1; these cases are now handled
differently to begin with.
This patch removes the parameter and the code in SelectSETCC that
attempted to handle the Other != -1 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185541
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Craig Topper [Wed, 3 Jul 2013 15:07:05 +0000 (15:07 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540
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Craig Topper [Wed, 3 Jul 2013 14:48:37 +0000 (14:48 +0000)]
Fix regular expression used by 'make update' to only look for 'I' and '?' at the start of svn info results and to check for spaces after 'I' instead of just after '?'.
Previously it was able to match 'I' anywhere in the filenames of the svn info results instead of just files that where ignored or unknown to svn. This would cause 'make update' to infinitely recurse if a file was modified with I anywhere in its name since svn info would return a Path pointing to the llvm root for those files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185539
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Evgeniy Stepanov [Wed, 3 Jul 2013 14:39:14 +0000 (14:39 +0000)]
[msan] Unpoison stack allocations and undef values in blacklisted functions.
This changes behavior of -msan-poison-stack=0 flag from not poisoning stack
allocations to actively unpoisoning them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185538
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Ulrich Weigand [Wed, 3 Jul 2013 12:51:09 +0000 (12:51 +0000)]
[PowerPC] Make specialized AltiVec patterns isCodeGenOnly
A couple of AltiVec patterns are just specialized forms of the
generic instruction pattern, and should therefore be marked
isCodeGenOnly to avoid confusing the asm parser:
VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES.
Noticed by inspection of the generated PPCGenAsmMatcher.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185533
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Ulrich Weigand [Wed, 3 Jul 2013 12:32:41 +0000 (12:32 +0000)]
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532
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Richard Sandiford [Wed, 3 Jul 2013 10:10:02 +0000 (10:10 +0000)]
[SystemZ] Fold more spills
Add a mapping from register-based <INSN>R instructions to the corresponding
memory-based <INSN>. Use it to cut down on the number of spill loads.
Some instructions extend their operands from smaller fields, so this
required a new TSFlags field to say how big the unextended operand is.
This optimisation doesn't trigger for C(G)R and CL(G)R because in practice
we always combine those instructions with a branch. Adding a test for every
other case probably seems excessive, but it did catch a missed optimisation
for DSGF (fixed in r185435).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529
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Mihai Popa [Wed, 3 Jul 2013 09:21:44 +0000 (09:21 +0000)]
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528
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Tim Northover [Wed, 3 Jul 2013 09:20:36 +0000 (09:20 +0000)]
ARM: relax the atomic release barrier to "dmb ishst" on Swift
Swift cores implement store barriers that are stronger than the ARM
specification but weaker than general barriers. They are, in fact, just about
enough to provide the ordering needed for atomic operations with release
semantics.
This patch makes use of that quirk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527
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Richard Sandiford [Wed, 3 Jul 2013 09:19:58 +0000 (09:19 +0000)]
[SystemZ] Rename mapping table fields
Rename Function->DispKey and PairType->DispSize. I'd originally used
"Function" because I thought it might be useful for other InstMappings.
However, it turns out that having two very similar instructions with the
same Function makes it pretty useless for anything other than the displacement
size key. Other InstMappings will want the key to be defined for only one
instruction in the pair.
No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185526
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Richard Sandiford [Wed, 3 Jul 2013 09:11:00 +0000 (09:11 +0000)]
[SystemZ] Fix caller-allocated save slot FIXME
Get rid of some old code (and associated FIXME) for handling the
caller-allocated register save area. No behavioural change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185525
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Eric Christopher [Wed, 3 Jul 2013 08:26:07 +0000 (08:26 +0000)]
Remove unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185523
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Eric Christopher [Wed, 3 Jul 2013 08:13:55 +0000 (08:13 +0000)]
Constify a few functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185520
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Richard Osborne [Wed, 3 Jul 2013 07:49:03 +0000 (07:49 +0000)]
[XCore] Whitespace fixes, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185519
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Richard Osborne [Wed, 3 Jul 2013 07:48:50 +0000 (07:48 +0000)]
[XCore] Add ISel pattern for LDWCP
Patch by Robert Lytton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185518
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Craig Topper [Wed, 3 Jul 2013 05:18:47 +0000 (05:18 +0000)]
Use SmallVectorImpl::const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185514
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Craig Topper [Wed, 3 Jul 2013 05:16:59 +0000 (05:16 +0000)]
Use SmallVectorImpl instead of SmallVector as method argument to avoid specifying vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185513
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Craig Topper [Wed, 3 Jul 2013 05:11:49 +0000 (05:11 +0000)]
Use SmallVectorImpl instead of SmallVector for iterators and references to avoid specifying the vector size unnecessarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185512
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Eric Christopher [Wed, 3 Jul 2013 05:01:24 +0000 (05:01 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector
to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185511
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Craig Topper [Wed, 3 Jul 2013 04:42:33 +0000 (04:42 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185509
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Craig Topper [Wed, 3 Jul 2013 04:40:27 +0000 (04:40 +0000)]
Introduce some typedefs for DenseMaps containing SmallVectors so the vector size doesn't have to repeated when creating iterators for the DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185508
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Craig Topper [Wed, 3 Jul 2013 04:30:58 +0000 (04:30 +0000)]
Return SmallVectorImpl& instead of SmallVector& in a couple places to avoid having to specify the vector size in multiple places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185507
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Craig Topper [Wed, 3 Jul 2013 04:27:31 +0000 (04:27 +0000)]
Add a space between type and variable name. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185506
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Craig Topper [Wed, 3 Jul 2013 04:24:43 +0000 (04:24 +0000)]
Use SmallVectorImpl& instead of SmallVector& to avoid needlessly respecifying the small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185505
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Craig Topper [Wed, 3 Jul 2013 04:17:25 +0000 (04:17 +0000)]
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185504
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Michael Gottesman [Wed, 3 Jul 2013 04:15:22 +0000 (04:15 +0000)]
Change the gettimeofday test to only test on a posix platform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185503
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Michael Gottesman [Wed, 3 Jul 2013 04:00:54 +0000 (04:00 +0000)]
Added support in FunctionAttrs for adding relevant function/argument attributes for the posix call gettimeofday.
This implies annotating it as nounwind and its arguments as nocapture. To be
conservative, we do not annotate the arguments with noalias since some platforms
do not have restrict on the declaration for gettimeofday.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185502
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