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(parent: 67cfc20) | patch
drm/i915: Include display_mmio_offset in sequencer index/data registers
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 25 Jan 2013 19:44:45 +0000 (21:44 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sat, 26 Jan 2013 16:32:03 +0000 (17:32 +0100)
commit56a12a509296c87d6f149be86c6694d312b21d35
treed50eb6be8db694c3ef35884b7d1c28991d83a6d4tree | snapshot
parent67cfc2032b516e44b972abe30209234343e1f145commit | diff
drm/i915: Include display_mmio_offset in sequencer index/data registers

SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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