Programming Languages Research Group: Git - firefly-linux-kernel-4.4.55.git/blob

1 /*

2 * This file is dual-licensed: you can use it either under the terms

3 * of the GPL or the X11 license, at your option. Note that this dual

4 * licensing only applies to this file, and not this project as a

5 * whole.

6 *

7 * a) This file is free software; you can redistribute it and/or

8 * modify it under the terms of the GNU General Public License as

9 * published by the Free Software Foundation; either version 2 of the

10 * License, or (at your option) any later version.

11 *

12 * This file is distributed in the hope that it will be useful,

13 * but WITHOUT ANY WARRANTY; without even the implied warranty of

14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

15 * GNU General Public License for more details.

16 *

17 * Or, alternatively,

18 *

19 * b) Permission is hereby granted, free of charge, to any person

20 * obtaining a copy of this software and associated documentation

21 * files (the "Software"), to deal in the Software without

22 * restriction, including without limitation the rights to use,

23 * copy, modify, merge, publish, distribute, sublicense, and/or

24 * sell copies of the Software, and to permit persons to whom the

25 * Software is furnished to do so, subject to the following

26 * conditions:

27 *

28 * The above copyright notice and this permission notice shall be

29 * included in all copies or substantial portions of the Software.

30 *

31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES

33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND

34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT

35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

38 * OTHER DEALINGS IN THE SOFTWARE.

39 */

40

41 #include <dt-bindings/gpio/gpio.h>

42 #include <dt-bindings/interrupt-controller/irq.h>

43 #include <dt-bindings/interrupt-controller/arm-gic.h>

44 #include <dt-bindings/pinctrl/rockchip.h>

45 #include <dt-bindings/clock/rk3228-cru.h>

46 #include <dt-bindings/thermal/thermal.h>

47 #include "skeleton.dtsi"

48

49 / {

50 interrupt-parent = <&gic>;

51

52 aliases {

53 serial0 = &uart0;

54 serial1 = &uart1;

55 serial2 = &uart2;

56 };

57

58 cpus {

59 #address-cells = <1>;

60 #size-cells = <0>;

61

62 cpu0: cpu@f00 {

63 device_type = "cpu";

64 compatible = "arm,cortex-a7";

65 reg = <0xf00>;

66 resets = <&cru SRST_CORE0>;

67 operating-points-v2 = <&cpu0_opp_table>;

68 #cooling-cells = <2>; /* min followed by max */

69 clock-latency = <40000>;

70 clocks = <&cru ARMCLK>;

71 };

72

73 cpu1: cpu@f01 {

74 device_type = "cpu";

75 compatible = "arm,cortex-a7";

76 reg = <0xf01>;

77 resets = <&cru SRST_CORE1>;

78 operating-points-v2 = <&cpu0_opp_table>;

79 };

80

81 cpu2: cpu@f02 {

82 device_type = "cpu";

83 compatible = "arm,cortex-a7";

84 reg = <0xf02>;

85 resets = <&cru SRST_CORE2>;

86 operating-points-v2 = <&cpu0_opp_table>;

87 };

88

89 cpu3: cpu@f03 {

90 device_type = "cpu";

91 compatible = "arm,cortex-a7";

92 reg = <0xf03>;

93 resets = <&cru SRST_CORE3>;

94 operating-points-v2 = <&cpu0_opp_table>;

95 };

96 };

97

98 cpu0_opp_table: opp_table0 {

99 compatible = "operating-points-v2";

100 opp-shared;

101

102 nvmem-cells = <&cpu_leakage>;

103 nvmem-cell-names = "cpu_leakage";

104

105 opp-408000000 {

106 opp-hz = /bits/ 64 <408000000>;

107 opp-microvolt = <950000>;

108 clock-latency-ns = <40000>;

109 opp-suspend;

110 };

111 opp-600000000 {

112 opp-hz = /bits/ 64 <600000000>;

113 opp-microvolt = <975000>;

114 };

115 opp-816000000 {

116 opp-hz = /bits/ 64 <816000000>;

117 opp-microvolt = <1000000>;

118 };

119 opp-1008000000 {

120 opp-hz = /bits/ 64 <1008000000>;

121 opp-microvolt = <1175000>;

122 };

123 opp-1200000000 {

124 opp-hz = /bits/ 64 <1200000000>;

125 opp-microvolt = <1275000>;

126 };

127 };

128

129 amba {

130 compatible = "arm,amba-bus";

131 #address-cells = <1>;

132 #size-cells = <1>;

133 ranges;

134

135 pdma: pdma@110f0000 {

136 compatible = "arm,pl330", "arm,primecell";

137 reg = <0x110f0000 0x4000>;

138 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

139 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

140 #dma-cells = <1>;

141 clocks = <&cru ACLK_DMAC>;

142 clock-names = "apb_pclk";

143 };

144 };

145

146 arm-pmu {

147 compatible = "arm,cortex-a7-pmu";

148 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

149 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,

150 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,

151 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

152 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;

153 };

154

155 timer {

156 compatible = "arm,armv7-timer";

157 arm,cpu-registers-not-fw-configured;

158 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,

159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,

160 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,

161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

162 clock-frequency = <24000000>;

163 };

164

165 xin24m: oscillator {

166 compatible = "fixed-clock";

167 clock-frequency = <24000000>;

168 clock-output-names = "xin24m";

169 #clock-cells = <0>;

170 };

171

172 i2s1: i2s1@100b0000 {

173 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";

174 reg = <0x100b0000 0x4000>;

175 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

176 #address-cells = <1>;

177 #size-cells = <0>;

178 clock-names = "i2s_clk", "i2s_hclk";

179 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;

180 dmas = <&pdma 14>, <&pdma 15>;

181 dma-names = "tx", "rx";

182 pinctrl-names = "default";

183 pinctrl-0 = <&i2s1_bus>;

184 status = "disabled";

185 };

186

187 i2s0: i2s0@100c0000 {

188 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";

189 reg = <0x100c0000 0x4000>;

190 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

191 #address-cells = <1>;

192 #size-cells = <0>;

193 clock-names = "i2s_clk", "i2s_hclk";

194 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;

195 dmas = <&pdma 11>, <&pdma 12>;

196 dma-names = "tx", "rx";

197 status = "disabled";

198 };

199

200 spdif: spdif@100d0000 {

201 compatible = "rockchip,rk3228-spdif";

202 reg = <0x100d0000 0x1000>;

203 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

204 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;

205 clock-names = "mclk", "hclk";

206 dmas = <&pdma 10>;

207 #dma-cells = <1>;

208 dma-names = "tx";

209 pinctrl-names = "default";

210 pinctrl-0 = <&spdif_tx>;

211 status = "disabled";

212 };

213

214 i2s2: i2s2@100e0000 {

215 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";

216 reg = <0x100e0000 0x4000>;

217 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

218 #address-cells = <1>;

219 #size-cells = <0>;

220 clock-names = "i2s_clk", "i2s_hclk";

221 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;

222 dmas = <&pdma 0>, <&pdma 1>;

223 dma-names = "tx", "rx";

224 status = "disabled";

225 };

226

227 grf: syscon@11000000 {

228 compatible = "syscon", "simple-mfd";

229 reg = <0x11000000 0x1000>;

230 #address-cells = <1>;

231 #size-cells = <1>;

232

233 io_domains: io-domains {

234 compatible = "rockchip,rk322x-io-voltage-domain";

235 status = "disabled";

236 };

237

238 u2phy0: usb2-phy@760 {

239 compatible = "rockchip,rk322x-usb2phy";

240 reg = <0x0760 0x0c>;

241 clocks = <&cru SCLK_OTGPHY0>;

242 clock-names = "phyclk";

243 #clock-cells = <0>;

244 clock-output-names = "usb480m_phy0";

245 status = "disabled";

246

247 u2phy0_otg: otg-port {

248 #phy-cells = <0>;

249 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

250 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

251 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;

252 interrupt-names = "otg-bvalid", "otg-id",

253 "linestate";

254 status = "disabled";

255 };

256

257 u2phy0_host: host-port {

258 #phy-cells = <0>;

259 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

260 interrupt-names = "linestate";

261 status = "disabled";

262 };

263 };

264

265 u2phy1: usb2-phy@800 {

266 compatible = "rockchip,rk322x-usb2phy";

267 reg = <0x0800 0x0c>;

268 clocks = <&cru SCLK_OTGPHY1>;

269 clock-names = "phyclk";

270 #clock-cells = <0>;

271 clock-output-names = "usb480m_phy1";

272 status = "disabled";

273

274 u2phy1_host: host-port {

275 #phy-cells = <0>;

276 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

277 interrupt-names = "linestate";

278 status = "disabled";

279 };

280 };

281 };

282

283 uart0: serial@11010000 {

284 compatible = "snps,dw-apb-uart";

285 reg = <0x11010000 0x100>;

286 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

287 clock-frequency = <24000000>;

288 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;

289 clock-names = "baudclk", "apb_pclk";

290 pinctrl-names = "default";

291 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;

292 reg-shift = <2>;

293 reg-io-width = <4>;

294 status = "disabled";

295 };

296

297 uart1: serial@11020000 {

298 compatible = "snps,dw-apb-uart";

299 reg = <0x11020000 0x100>;

300 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

301 clock-frequency = <24000000>;

302 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;

303 clock-names = "baudclk", "apb_pclk";

304 pinctrl-names = "default";

305 pinctrl-0 = <&uart1_xfer>;

306 reg-shift = <2>;

307 reg-io-width = <4>;

308 status = "disabled";

309 };

310

311 uart2: serial@11030000 {

312 compatible = "snps,dw-apb-uart";

313 reg = <0x11030000 0x100>;

314 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;

315 clock-frequency = <24000000>;

316 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;

317 clock-names = "baudclk", "apb_pclk";

318 pinctrl-names = "default";

319 pinctrl-0 = <&uart21_xfer>;

320 reg-shift = <2>;

321 reg-io-width = <4>;

322 status = "disabled";

323 };

324

325 efuse: efuse@11040000 {

326 compatible = "rockchip,rk322x-efuse";

327 reg = <0x11040000 0x20>;

328 #address-cells = <1>;

329 #size-cells = <1>;

330 clocks = <&cru PCLK_EFUSE_256>;

331 clock-names = "pclk_efuse";

332

333 /* Data cells */

334 efuse_id: id@7 {

335 reg = <0x7 0x10>;

336 };

337 cpu_leakage: cpu_leakage@17 {

338 reg = <0x17 0x1>;

339 };

340 };

341

342 i2c0: i2c@11050000 {

343 compatible = "rockchip,rk3228-i2c";

344 reg = <0x11050000 0x1000>;

345 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

346 #address-cells = <1>;

347 #size-cells = <0>;

348 clock-names = "i2c";

349 clocks = <&cru PCLK_I2C0>;

350 pinctrl-names = "default";

351 pinctrl-0 = <&i2c0_xfer>;

352 status = "disabled";

353 };

354

355 i2c1: i2c@11060000 {

356 compatible = "rockchip,rk3228-i2c";

357 reg = <0x11060000 0x1000>;

358 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

359 #address-cells = <1>;

360 #size-cells = <0>;

361 clock-names = "i2c";

362 clocks = <&cru PCLK_I2C1>;

363 pinctrl-names = "default";

364 pinctrl-0 = <&i2c1_xfer>;

365 status = "disabled";

366 };

367

368 i2c2: i2c@11070000 {

369 compatible = "rockchip,rk3228-i2c";

370 reg = <0x11070000 0x1000>;

371 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

372 #address-cells = <1>;

373 #size-cells = <0>;

374 clock-names = "i2c";

375 clocks = <&cru PCLK_I2C2>;

376 pinctrl-names = "default";

377 pinctrl-0 = <&i2c2_xfer>;

378 status = "disabled";

379 };

380

381 i2c3: i2c@11080000 {

382 compatible = "rockchip,rk3228-i2c";

383 reg = <0x11080000 0x1000>;

384 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

385 #address-cells = <1>;

386 #size-cells = <0>;

387 clock-names = "i2c";

388 clocks = <&cru PCLK_I2C3>;

389 pinctrl-names = "default";

390 pinctrl-0 = <&i2c3_xfer>;

391 status = "disabled";

392 };

393

394 wdt: watchdog@110a0000 {

395 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";

396 reg = <0x110a0000 0x100>;

397 clocks = <&cru PCLK_CPU>;

398 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

399 status = "disabled";

400 };

401

402 pwm0: pwm@110b0000 {

403 compatible = "rockchip,rk3288-pwm";

404 reg = <0x110b0000 0x10>;

405 #pwm-cells = <3>;

406 clocks = <&cru PCLK_PWM>;

407 clock-names = "pwm";

408 pinctrl-names = "default";

409 pinctrl-0 = <&pwm0_pin>;

410 status = "disabled";

411 };

412

413 pwm1: pwm@110b0010 {

414 compatible = "rockchip,rk3288-pwm";

415 reg = <0x110b0010 0x10>;

416 #pwm-cells = <3>;

417 clocks = <&cru PCLK_PWM>;

418 clock-names = "pwm";

419 pinctrl-names = "default";

420 pinctrl-0 = <&pwm1_pin>;

421 status = "disabled";

422 };

423

424 pwm2: pwm@110b0020 {

425 compatible = "rockchip,rk3288-pwm";

426 reg = <0x110b0020 0x10>;

427 #pwm-cells = <3>;

428 clocks = <&cru PCLK_PWM>;

429 clock-names = "pwm";

430 pinctrl-names = "default";

431 pinctrl-0 = <&pwm2_pin>;

432 status = "disabled";

433 };

434

435 pwm3: pwm@110b0030 {

436 compatible = "rockchip,rk3288-pwm";

437 reg = <0x110b0030 0x10>;

438 #pwm-cells = <2>;

439 clocks = <&cru PCLK_PWM>;

440 clock-names = "pwm";

441 pinctrl-names = "default";

442 pinctrl-0 = <&pwm3_pin>;

443 status = "disabled";

444 };

445

446 timer: timer@110c0000 {

447 compatible = "rockchip,rk3288-timer";

448 reg = <0x110c0000 0x20>;

449 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;

450 clocks = <&xin24m>, <&cru PCLK_TIMER>;

451 clock-names = "timer", "pclk";

452 };

453

454 cru: clock-controller@110e0000 {

455 compatible = "rockchip,rk3228-cru";

456 reg = <0x110e0000 0x1000>;

457 rockchip,grf = <&grf>;

458 #clock-cells = <1>;

459 #reset-cells = <1>;

460 assigned-clocks =

461 <&cru PLL_GPLL>, <&cru ARMCLK>,

462 <&cru PLL_CPLL>, <&cru ACLK_PERI>,

463 <&cru HCLK_PERI>, <&cru PCLK_PERI>,

464 <&cru ACLK_CPU>, <&cru HCLK_CPU>,

465 <&cru PCLK_CPU>;

466 assigned-clock-rates =

467 <594000000>, <816000000>,

468 <500000000>, <150000000>,

469 <150000000>, <75000000>,

470 <150000000>, <150000000>,

471 <75000000>;

472 };

473

474 thermal-zones {

475 cpu_thermal: cpu-thermal {

476 polling-delay-passive = <100>; /* milliseconds */

477 polling-delay = <5000>; /* milliseconds */

478

479 thermal-sensors = <&tsadc 0>;

480

481 trips {

482 cpu_alert0: cpu_alert0 {

483 temperature = <70000>; /* millicelsius */

484 hysteresis = <2000>; /* millicelsius */

485 type = "passive";

486 };

487 cpu_alert1: cpu_alert1 {

488 temperature = <75000>; /* millicelsius */

489 hysteresis = <2000>; /* millicelsius */

490 type = "passive";

491 };

492 cpu_crit: cpu_crit {

493 temperature = <90000>; /* millicelsius */

494 hysteresis = <2000>; /* millicelsius */

495 type = "critical";

496 };

497 };

498

499 cooling-maps {

500 map0 {

501 trip = <&cpu_alert0>;

502 cooling-device =

503 <&cpu0 THERMAL_NO_LIMIT 6>;

504 };

505 map1 {

506 trip = <&cpu_alert1>;

507 cooling-device =

508 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

509 };

510 };

511 };

512 };

513

514 tsadc: tsadc@11150000 {

515 compatible = "rockchip,rk3228-tsadc";

516 reg = <0x11150000 0x100>;

517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;

518 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;

519 clock-names = "tsadc", "apb_pclk";

520 resets = <&cru SRST_TSADC>;

521 reset-names = "tsadc-apb";

522 pinctrl-names = "init", "default", "sleep";

523 pinctrl-0 = <&otp_gpio>;

524 pinctrl-1 = <&otp_out>;

525 pinctrl-2 = <&otp_gpio>;

526 #thermal-sensor-cells = <0>;

527 rockchip,hw-tshut-temp = <95000>;

528 status = "disabled";

529 };

530

531 gpu: gpu@0x20001000 {

532 compatible = "arm,mali400";

533 reg = <0x20001000 0x200>,

534 <0x20000000 0x100>,

535 <0x20003000 0x100>,

536 <0x20008000 0x1100>,

537 <0x20004000 0x100>,

538 <0x2000A000 0x1100>,

539 <0x20005000 0x100>;

540

541 reg-names = "Mali_L2",

542 "Mali_GP",

543 "Mali_GP_MMU",

544 "Mali_PP0",

545 "Mali_PP0_MMU",

546 "Mali_PP1",

547 "Mali_PP1_MMU";

548

549 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

550 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

551 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

552 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

553 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

554 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

555

556 interrupt-names = "Mali_GP_IRQ",

557 "Mali_GP_MMU_IRQ",

558 "Mali_PP0_IRQ",

559 "Mali_PP0_MMU_IRQ",

560 "Mali_PP1_IRQ",

561 "Mali_PP1_MMU_IRQ";

562 clocks = <&cru ACLK_GPU>;

563 clock-names = "clk_mali";

564 operating-points-v2 = <&gpu_opp_table>;

565 status = "disabled";

566 };

567

568 gpu_opp_table: opp-table2 {

569 compatible = "operating-points-v2";

570

571 opp-200000000 {

572 opp-hz = /bits/ 64 <200000000>;

573 opp-microvolt = <1050000>;

574 };

575 opp-300000000 {

576 opp-hz = /bits/ 64 <300000000>;

577 opp-microvolt = <1050000>;

578 };

579 opp-500000000 {

580 opp-hz = /bits/ 64 <500000000>;

581 opp-microvolt = <1150000>;

582 };

583 };

584

585 vop: vop@20050000 {

586 compatible = "rockchip,rk322x-vop";

587 reg = <0x20050000 0x1ffc>, <0x20052000 0x1000>;

588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

589 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;

590 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

591 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;

592 reset-names = "axi", "ahb", "dclk";

593 iommus = <&vop_mmu>;

594 status = "disabled";

595

596 vop_out: port {

597 #address-cells = <1>;

598 #size-cells = <0>;

599 };

600 };

601

602 vop_mmu: iommu@20050300 {

603 compatible = "rockchip,iommu";

604 reg = <0x20053f00 0x100>;

605 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

606 interrupt-names = "vop_mmu";

607 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;

608 clock-names = "aclk", "hclk";

609 #iommu-cells = <0>;

610 status = "disabled";

611 };

612

613 display-subsystem {

614 compatible = "rockchip,display-subsystem";

615 ports = <&vop_out>;

616 };

617

618 emmc: dwmmc@30020000 {

619 compatible = "rockchip,rk3288-dw-mshc";

620 reg = <0x30020000 0x4000>;

621 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

622 clock-frequency = <37500000>;

623 clock-freq-min-max = <400000 37500000>;

624 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

625 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;

626 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";

627 bus-width = <8>;

628 default-sample-phase = <158>;

629 num-slots = <1>;

630 fifo-depth = <0x100>;

631 pinctrl-names = "default";

632 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;

633 status = "disabled";

634 };

635

636 usb_otg: usb@30040000 {

637 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",

638 "snps,dwc2";

639 reg = <0x30040000 0x40000>;

640 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

641 clocks = <&cru HCLK_OTG>;

642 clock-names = "otg";

643 dr_mode = "otg";

644 g-np-tx-fifo-size = <16>;

645 g-rx-fifo-size = <275>;

646 g-tx-fifo-size = <256 128 128 64 64 32>;

647 g-use-dma;

648 phys = <&u2phy0_otg>;

649 phy-names = "usb2-phy";

650 status = "disabled";

651 };

652

653 usb_host0_ehci: usb@30080000 {

654 compatible = "generic-ehci";

655 reg = <0x30080000 0x20000>;

656 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

657 clocks = <&cru HCLK_HOST0>, <&u2phy0>;

658 clock-names = "usbhost", "utmi";

659 phys = <&u2phy0_host>;

660 phy-names = "usb";

661 status = "disabled";

662 };

663

664 usb_host0_ohci: usb@300a0000 {

665 compatible = "generic-ohci";

666 reg = <0x300a0000 0x20000>;

667 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

668 clocks = <&cru HCLK_HOST0>, <&u2phy0>;

669 clock-names = "usbhost", "utmi";

670 phys = <&u2phy0_host>;

671 phy-names = "usb";

672 status = "disabled";

673 };

674

675 usb_host1_ehci: usb@300c0000 {

676 compatible = "generic-ehci";

677 reg = <0x300c0000 0x20000>;

678 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

679 clocks = <&cru HCLK_HOST1>, <&u2phy1>;

680 clock-names = "usbhost", "utmi";

681 phys = <&u2phy1_host>;

682 phy-names = "usb";

683 status = "disabled";

684 };

685

686 usb_host1_ohci: usb@300e0000 {

687 compatible = "generic-ohci";

688 reg = <0x300e0000 0x20000>;

689 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

690 clocks = <&cru HCLK_HOST1>, <&u2phy1>;

691 clock-names = "usbhost", "utmi";

692 phys = <&u2phy1_host>;

693 phy-names = "usb";

694 status = "disabled";

695 };

696

697 usb_host2_ehci: usb@30100000 {

698 compatible = "generic-ehci";

699 reg = <0x30100000 0x20000>;

700 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

701 clocks = <&cru HCLK_HOST2>, <&u2phy1>;

702 clock-names = "usbhost", "utmi";

703 status = "disabled";

704 };

705

706 usb_host2_ohci: usb@30120000 {

707 compatible = "generic-ohci";

708 reg = <0x30120000 0x20000>;

709 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

710 clocks = <&cru HCLK_HOST2>, <&u2phy1>;

711 clock-names = "usbhost", "utmi";

712 status = "disabled";

713 };

714

715 gmac: ethernet@30200000 {

716 compatible = "rockchip,rk3228-gmac";

717 reg = <0x30200000 0x10000>;

718 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

719 interrupt-names = "macirq";

720 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,

721 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,

722 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,

723 <&cru PCLK_GMAC>;

724 clock-names = "stmmaceth", "mac_clk_rx",

725 "mac_clk_tx", "clk_mac_ref",

726 "clk_mac_refout", "aclk_mac",

727 "pclk_mac";

728 resets = <&cru SRST_GMAC>;

729 reset-names = "stmmaceth";

730 rockchip,grf = <&grf>;

731 status = "disabled";

732 };

733

734 gic: interrupt-controller@32010000 {

735 compatible = "arm,gic-400";

736 interrupt-controller;

737 #interrupt-cells = <3>;

738 #address-cells = <0>;

739

740 reg = <0x32011000 0x1000>,

741 <0x32012000 0x2000>,

742 <0x32014000 0x2000>,

743 <0x32016000 0x2000>;

744 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

745 };

746

747 pinctrl: pinctrl {

748 compatible = "rockchip,rk3228-pinctrl";

749 rockchip,grf = <&grf>;

750 #address-cells = <1>;

751 #size-cells = <1>;

752 ranges;

753

754 gpio0: gpio0@11110000 {

755 compatible = "rockchip,gpio-bank";

756 reg = <0x11110000 0x100>;

757 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

758 clocks = <&cru PCLK_GPIO0>;

759

760 gpio-controller;

761 #gpio-cells = <2>;

762

763 interrupt-controller;

764 #interrupt-cells = <2>;

765 };

766

767 gpio1: gpio1@11120000 {

768 compatible = "rockchip,gpio-bank";

769 reg = <0x11120000 0x100>;

770 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

771 clocks = <&cru PCLK_GPIO1>;

772

773 gpio-controller;

774 #gpio-cells = <2>;

775

776 interrupt-controller;

777 #interrupt-cells = <2>;

778 };

779

780 gpio2: gpio2@11130000 {

781 compatible = "rockchip,gpio-bank";

782 reg = <0x11130000 0x100>;

783 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;

784 clocks = <&cru PCLK_GPIO2>;

785

786 gpio-controller;

787 #gpio-cells = <2>;

788

789 interrupt-controller;

790 #interrupt-cells = <2>;

791 };

792

793 gpio3: gpio3@11140000 {

794 compatible = "rockchip,gpio-bank";

795 reg = <0x11140000 0x100>;

796 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

797 clocks = <&cru PCLK_GPIO3>;

798

799 gpio-controller;

800 #gpio-cells = <2>;

801

802 interrupt-controller;

803 #interrupt-cells = <2>;

804 };

805

806 pcfg_pull_up: pcfg-pull-up {

807 bias-pull-up;

808 };

809

810 pcfg_pull_down: pcfg-pull-down {

811 bias-pull-down;

812 };

813

814 pcfg_pull_none: pcfg-pull-none {

815 bias-disable;

816 };

817

818 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {

819 drive-strength = <12>;

820 };

821

822 emmc {

823 emmc_clk: emmc-clk {

824 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;

825 };

826

827 emmc_cmd: emmc-cmd {

828 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;

829 };

830

831 emmc_bus8: emmc-bus8 {

832 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,

833 <1 25 RK_FUNC_2 &pcfg_pull_none>,

834 <1 26 RK_FUNC_2 &pcfg_pull_none>,

835 <1 27 RK_FUNC_2 &pcfg_pull_none>,

836 <1 28 RK_FUNC_2 &pcfg_pull_none>,

837 <1 29 RK_FUNC_2 &pcfg_pull_none>,

838 <1 30 RK_FUNC_2 &pcfg_pull_none>,

839 <1 31 RK_FUNC_2 &pcfg_pull_none>;

840 };

841 };

842

843 gmac {

844 rgmii_pins: rgmii-pins {

845 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,

846 <2 12 RK_FUNC_1 &pcfg_pull_none>,

847 <2 25 RK_FUNC_1 &pcfg_pull_none>,

848 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

849 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

850 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

851 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

852 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

853 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

854 <2 17 RK_FUNC_1 &pcfg_pull_none>,

855 <2 16 RK_FUNC_1 &pcfg_pull_none>,

856 <2 21 RK_FUNC_2 &pcfg_pull_none>,

857 <2 20 RK_FUNC_2 &pcfg_pull_none>,

858 <2 11 RK_FUNC_1 &pcfg_pull_none>,

859 <2 8 RK_FUNC_1 &pcfg_pull_none>;

860 };

861

862 rmii_pins: rmii-pins {

863 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,

864 <2 12 RK_FUNC_1 &pcfg_pull_none>,

865 <2 25 RK_FUNC_1 &pcfg_pull_none>,

866 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

867 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

868 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,

869 <2 17 RK_FUNC_1 &pcfg_pull_none>,

870 <2 16 RK_FUNC_1 &pcfg_pull_none>,

871 <2 8 RK_FUNC_1 &pcfg_pull_none>,

872 <2 15 RK_FUNC_1 &pcfg_pull_none>;

873 };

874

875 phy_pins: phy-pins {

876 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,

877 <2 8 RK_FUNC_2 &pcfg_pull_none>;

878 };

879 };

880

881 i2c0 {

882 i2c0_xfer: i2c0-xfer {

883 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,

884 <0 1 RK_FUNC_1 &pcfg_pull_none>;

885 };

886 };

887

888 i2c1 {

889 i2c1_xfer: i2c1-xfer {

890 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,

891 <0 3 RK_FUNC_1 &pcfg_pull_none>;

892 };

893 };

894

895 i2c2 {

896 i2c2_xfer: i2c2-xfer {

897 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,

898 <2 21 RK_FUNC_1 &pcfg_pull_none>;

899 };

900 };

901

902 i2c3 {

903 i2c3_xfer: i2c3-xfer {

904 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,

905 <0 7 RK_FUNC_1 &pcfg_pull_none>;

906 };

907 };

908

909 i2s1 {

910 i2s1_bus: i2s1-bus {

911 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,

912 <0 9 RK_FUNC_1 &pcfg_pull_none>,

913 <0 11 RK_FUNC_1 &pcfg_pull_none>,

914 <0 12 RK_FUNC_1 &pcfg_pull_none>,

915 <0 13 RK_FUNC_1 &pcfg_pull_none>,

916 <0 14 RK_FUNC_1 &pcfg_pull_none>,

917 <1 2 RK_FUNC_1 &pcfg_pull_none>,

918 <1 4 RK_FUNC_1 &pcfg_pull_none>,

919 <1 5 RK_FUNC_1 &pcfg_pull_none>;

920 };

921 };

922

923 pwm0 {

924 pwm0_pin: pwm0-pin {

925 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;

926 };

927 };

928

929 pwm1 {

930 pwm1_pin: pwm1-pin {

931 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;

932 };

933 };

934

935 pwm2 {

936 pwm2_pin: pwm2-pin {

937 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;

938 };

939 };

940

941 pwm3 {

942 pwm3_pin: pwm3-pin {

943 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;

944 };

945 };

946

947 spdif {

948 spdif_tx: spdif-tx {

949 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;

950 };

951 };

952

953 tsadc {

954 otp_gpio: otp-gpio {

955 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;

956 };

957

958 otp_out: otp-out {

959 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;

960 };

961 };

962

963 uart0 {

964 uart0_xfer: uart0-xfer {

965 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,

966 <2 27 RK_FUNC_1 &pcfg_pull_none>;

967 };

968

969 uart0_cts: uart0-cts {

970 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;

971 };

972

973 uart0_rts: uart0-rts {

974 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;

975 };

976 };

977

978 uart1 {

979 uart1_xfer: uart1-xfer {

980 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,

981 <1 10 RK_FUNC_1 &pcfg_pull_none>;

982 };

983

984 uart1_cts: uart1-cts {

985 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;

986 };

987

988 uart1_rts: uart1-rts {

989 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;

990 };

991 };

992

993 uart2 {

994 uart2_xfer: uart2-xfer {

995 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,

996 <1 19 RK_FUNC_2 &pcfg_pull_none>;

997 };

998

999 uart2_cts: uart2-cts {

1000 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;

1001 };

1002

1003 uart2_rts: uart2-rts {

1004 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;

1005 };

1006 };

1007

1008 uart2-1 {

1009 uart21_xfer: uart21-xfer {

1010 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,

1011 <1 9 RK_FUNC_2 &pcfg_pull_none>;

1012 };

1013 };

1014 };

1015 };