2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
23 int mindelta, int main_rssi_avg,
24 int alt_rssi_avg, int pkt_count)
26 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
27 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
28 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
33 return sc->ps_enabled &&
34 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
38 struct ieee80211_hdr *hdr)
40 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
43 spin_lock_bh(&sc->wiphy_lock);
44 for (i = 0; i < sc->num_sec_wiphy; i++) {
45 struct ath_wiphy *aphy = sc->sec_wiphy[i];
48 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
54 spin_unlock_bh(&sc->wiphy_lock);
59 * Setup and link descriptors.
61 * 11N: we can no longer afford to self link the last descriptor.
62 * MAC acknowledges BA status as long as it copies frames to host
63 * buffer (or rx fifo). This can incorrectly acknowledge packets
64 * to a sender if last desc is self-linked.
66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
68 struct ath_hw *ah = sc->sc_ah;
69 struct ath_common *common = ath9k_hw_common(ah);
76 ds->ds_link = 0; /* link to null */
77 ds->ds_data = bf->bf_buf_addr;
79 /* virtual addr of the beginning of the buffer. */
82 ds->ds_vdata = skb->data;
85 * setup rx descriptors. The rx_bufsize here tells the hardware
86 * how much data it can DMA to us and that we are prepared
89 ath9k_hw_setuprxdesc(ah, ds,
93 if (sc->rx.rxlink == NULL)
94 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
96 *sc->rx.rxlink = bf->bf_daddr;
98 sc->rx.rxlink = &ds->ds_link;
102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
104 /* XXX block beacon interrupts */
105 ath9k_hw_setantenna(sc->sc_ah, antenna);
106 sc->rx.defant = antenna;
107 sc->rx.rxotherant = 0;
110 static void ath_opmode_init(struct ath_softc *sc)
112 struct ath_hw *ah = sc->sc_ah;
113 struct ath_common *common = ath9k_hw_common(ah);
117 /* configure rx filter */
118 rfilt = ath_calcrxfilter(sc);
119 ath9k_hw_setrxfilter(ah, rfilt);
121 /* configure bssid mask */
122 ath_hw_setbssidmask(common);
124 /* configure operational mode */
125 ath9k_hw_setopmode(ah);
127 /* calculate and install multicast filter */
128 mfilt[0] = mfilt[1] = ~0;
129 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
133 enum ath9k_rx_qtype qtype)
135 struct ath_hw *ah = sc->sc_ah;
136 struct ath_rx_edma *rx_edma;
140 rx_edma = &sc->rx.rx_edma[qtype];
141 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
144 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
145 list_del_init(&bf->list);
150 memset(skb->data, 0, ah->caps.rx_status_len);
151 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
152 ah->caps.rx_status_len, DMA_TO_DEVICE);
154 SKB_CB_ATHBUF(skb) = bf;
155 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
156 skb_queue_tail(&rx_edma->rx_fifo, skb);
161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
162 enum ath9k_rx_qtype qtype, int size)
164 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
167 if (list_empty(&sc->rx.rxbuf)) {
168 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
172 while (!list_empty(&sc->rx.rxbuf)) {
175 if (!ath_rx_edma_buf_link(sc, qtype))
183 static void ath_rx_remove_buffer(struct ath_softc *sc,
184 enum ath9k_rx_qtype qtype)
187 struct ath_rx_edma *rx_edma;
190 rx_edma = &sc->rx.rx_edma[qtype];
192 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
193 bf = SKB_CB_ATHBUF(skb);
195 list_add_tail(&bf->list, &sc->rx.rxbuf);
199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
203 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
204 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
206 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
208 dev_kfree_skb_any(bf->bf_mpdu);
211 INIT_LIST_HEAD(&sc->rx.rxbuf);
213 kfree(sc->rx.rx_bufptr);
214 sc->rx.rx_bufptr = NULL;
217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
219 skb_queue_head_init(&rx_edma->rx_fifo);
220 skb_queue_head_init(&rx_edma->rx_buffers);
221 rx_edma->rx_fifo_hwsize = size;
224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
226 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227 struct ath_hw *ah = sc->sc_ah;
234 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
235 ah->caps.rx_status_len,
236 min(common->cachelsz, (u16)64));
238 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
239 ah->caps.rx_status_len);
241 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
242 ah->caps.rx_lp_qdepth);
243 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
244 ah->caps.rx_hp_qdepth);
246 size = sizeof(struct ath_buf) * nbufs;
247 bf = kzalloc(size, GFP_KERNEL);
251 INIT_LIST_HEAD(&sc->rx.rxbuf);
252 sc->rx.rx_bufptr = bf;
254 for (i = 0; i < nbufs; i++, bf++) {
255 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
261 memset(skb->data, 0, common->rx_bufsize);
264 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
267 if (unlikely(dma_mapping_error(sc->dev,
269 dev_kfree_skb_any(skb);
272 ath_print(common, ATH_DBG_FATAL,
273 "dma_mapping_error() on RX init\n");
278 list_add_tail(&bf->list, &sc->rx.rxbuf);
284 ath_rx_edma_cleanup(sc);
288 static void ath_edma_start_recv(struct ath_softc *sc)
290 spin_lock_bh(&sc->rx.rxbuflock);
292 ath9k_hw_rxena(sc->sc_ah);
294 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
295 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
297 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
298 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
302 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
304 spin_unlock_bh(&sc->rx.rxbuflock);
307 static void ath_edma_stop_recv(struct ath_softc *sc)
309 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
310 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
313 int ath_rx_init(struct ath_softc *sc, int nbufs)
315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
320 spin_lock_init(&sc->rx.rxflushlock);
321 sc->sc_flags &= ~SC_OP_RXFLUSH;
322 spin_lock_init(&sc->rx.rxbuflock);
324 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
325 return ath_rx_edma_init(sc, nbufs);
327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
328 min(common->cachelsz, (u16)64));
330 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
331 common->cachelsz, common->rx_bufsize);
333 /* Initialize rx descriptors */
335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
338 ath_print(common, ATH_DBG_FATAL,
339 "failed to allocate rx descriptors: %d\n",
344 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
353 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
356 if (unlikely(dma_mapping_error(sc->dev,
358 dev_kfree_skb_any(skb);
361 ath_print(common, ATH_DBG_FATAL,
362 "dma_mapping_error() on RX init\n");
367 sc->rx.rxlink = NULL;
377 void ath_rx_cleanup(struct ath_softc *sc)
379 struct ath_hw *ah = sc->sc_ah;
380 struct ath_common *common = ath9k_hw_common(ah);
384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
385 ath_rx_edma_cleanup(sc);
388 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
391 dma_unmap_single(sc->dev, bf->bf_buf_addr,
400 if (sc->rx.rxdma.dd_desc_len != 0)
401 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
406 * Calculate the receive filter according to the
407 * operating mode and state:
409 * o always accept unicast, broadcast, and multicast traffic
410 * o maintain current state of phy error reception (the hal
411 * may enable phy error frames for noise immunity work)
412 * o probe request frames are accepted only when operating in
413 * hostap, adhoc, or monitor modes
414 * o enable promiscuous mode according to the interface state
416 * - when operating in adhoc mode so the 802.11 layer creates
417 * node table entries for peers,
418 * - when operating in station mode for collecting rssi data when
419 * the station is otherwise quiet, or
420 * - when operating as a repeater so we see repeater-sta beacons
424 u32 ath_calcrxfilter(struct ath_softc *sc)
426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
430 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
431 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
432 | ATH9K_RX_FILTER_MCAST;
434 if (sc->rx.rxfilter & FIF_PROBE_REQ)
435 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
438 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
439 * mode interface or when in monitor mode. AP mode does not need this
440 * since it receives all in-BSS frames anyway.
442 if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
443 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
444 (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
445 rfilt |= ATH9K_RX_FILTER_PROM;
447 if (sc->rx.rxfilter & FIF_CONTROL)
448 rfilt |= ATH9K_RX_FILTER_CONTROL;
450 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
452 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
453 rfilt |= ATH9K_RX_FILTER_MYBEACON;
455 rfilt |= ATH9K_RX_FILTER_BEACON;
457 if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
458 AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
459 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
460 (sc->rx.rxfilter & FIF_PSPOLL))
461 rfilt |= ATH9K_RX_FILTER_PSPOLL;
463 if (conf_is_ht(&sc->hw->conf))
464 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
466 if (sc->sec_wiphy || (sc->nvifs > 1) ||
467 (sc->rx.rxfilter & FIF_OTHER_BSS)) {
468 /* The following may also be needed for other older chips */
469 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
470 rfilt |= ATH9K_RX_FILTER_PROM;
471 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
476 #undef RX_FILTER_PRESERVE
479 int ath_startrecv(struct ath_softc *sc)
481 struct ath_hw *ah = sc->sc_ah;
482 struct ath_buf *bf, *tbf;
484 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
485 ath_edma_start_recv(sc);
489 spin_lock_bh(&sc->rx.rxbuflock);
490 if (list_empty(&sc->rx.rxbuf))
493 sc->rx.rxlink = NULL;
494 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
495 ath_rx_buf_link(sc, bf);
498 /* We could have deleted elements so the list may be empty now */
499 if (list_empty(&sc->rx.rxbuf))
502 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
503 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
508 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
510 spin_unlock_bh(&sc->rx.rxbuflock);
515 bool ath_stoprecv(struct ath_softc *sc)
517 struct ath_hw *ah = sc->sc_ah;
520 spin_lock_bh(&sc->rx.rxbuflock);
521 ath9k_hw_stoppcurecv(ah);
522 ath9k_hw_setrxfilter(ah, 0);
523 stopped = ath9k_hw_stopdmarecv(ah);
525 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
526 ath_edma_stop_recv(sc);
528 sc->rx.rxlink = NULL;
529 spin_unlock_bh(&sc->rx.rxbuflock);
534 void ath_flushrecv(struct ath_softc *sc)
536 spin_lock_bh(&sc->rx.rxflushlock);
537 sc->sc_flags |= SC_OP_RXFLUSH;
538 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
539 ath_rx_tasklet(sc, 1, true);
540 ath_rx_tasklet(sc, 1, false);
541 sc->sc_flags &= ~SC_OP_RXFLUSH;
542 spin_unlock_bh(&sc->rx.rxflushlock);
545 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
547 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
548 struct ieee80211_mgmt *mgmt;
549 u8 *pos, *end, id, elen;
550 struct ieee80211_tim_ie *tim;
552 mgmt = (struct ieee80211_mgmt *)skb->data;
553 pos = mgmt->u.beacon.variable;
554 end = skb->data + skb->len;
556 while (pos + 2 < end) {
559 if (pos + elen > end)
562 if (id == WLAN_EID_TIM) {
563 if (elen < sizeof(*tim))
565 tim = (struct ieee80211_tim_ie *) pos;
566 if (tim->dtim_count != 0)
568 return tim->bitmap_ctrl & 0x01;
577 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
579 struct ieee80211_mgmt *mgmt;
580 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
582 if (skb->len < 24 + 8 + 2 + 2)
585 mgmt = (struct ieee80211_mgmt *)skb->data;
586 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
587 return; /* not from our current AP */
589 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
591 if (sc->ps_flags & PS_BEACON_SYNC) {
592 sc->ps_flags &= ~PS_BEACON_SYNC;
593 ath_print(common, ATH_DBG_PS,
594 "Reconfigure Beacon timers based on "
595 "timestamp from the AP\n");
596 ath_beacon_config(sc, NULL);
599 if (ath_beacon_dtim_pending_cab(skb)) {
601 * Remain awake waiting for buffered broadcast/multicast
602 * frames. If the last broadcast/multicast frame is not
603 * received properly, the next beacon frame will work as
604 * a backup trigger for returning into NETWORK SLEEP state,
605 * so we are waiting for it as well.
607 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
608 "buffered broadcast/multicast frame(s)\n");
609 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
613 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
615 * This can happen if a broadcast frame is dropped or the AP
616 * fails to send a frame indicating that all CAB frames have
619 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
620 ath_print(common, ATH_DBG_PS,
621 "PS wait for CAB frames timed out\n");
625 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
627 struct ieee80211_hdr *hdr;
628 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
630 hdr = (struct ieee80211_hdr *)skb->data;
632 /* Process Beacon and CAB receive in PS state */
633 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
634 && ieee80211_is_beacon(hdr->frame_control))
635 ath_rx_ps_beacon(sc, skb);
636 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
637 (ieee80211_is_data(hdr->frame_control) ||
638 ieee80211_is_action(hdr->frame_control)) &&
639 is_multicast_ether_addr(hdr->addr1) &&
640 !ieee80211_has_moredata(hdr->frame_control)) {
642 * No more broadcast/multicast frames to be received at this
645 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
646 ath_print(common, ATH_DBG_PS,
647 "All PS CAB frames received, back to sleep\n");
648 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
649 !is_multicast_ether_addr(hdr->addr1) &&
650 !ieee80211_has_morefrags(hdr->frame_control)) {
651 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
652 ath_print(common, ATH_DBG_PS,
653 "Going back to sleep after having received "
654 "PS-Poll data (0x%lx)\n",
655 sc->ps_flags & (PS_WAIT_FOR_BEACON |
657 PS_WAIT_FOR_PSPOLL_DATA |
658 PS_WAIT_FOR_TX_ACK));
662 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
663 struct ath_softc *sc, struct sk_buff *skb,
664 struct ieee80211_rx_status *rxs)
666 struct ieee80211_hdr *hdr;
668 hdr = (struct ieee80211_hdr *)skb->data;
670 /* Send the frame to mac80211 */
671 if (is_multicast_ether_addr(hdr->addr1)) {
674 * Deliver broadcast/multicast frames to all suitable
677 /* TODO: filter based on channel configuration */
678 for (i = 0; i < sc->num_sec_wiphy; i++) {
679 struct ath_wiphy *aphy = sc->sec_wiphy[i];
680 struct sk_buff *nskb;
683 nskb = skb_copy(skb, GFP_ATOMIC);
686 ieee80211_rx(aphy->hw, nskb);
688 ieee80211_rx(sc->hw, skb);
690 /* Deliver unicast frames based on receiver address */
691 ieee80211_rx(hw, skb);
694 static bool ath_edma_get_buffers(struct ath_softc *sc,
695 enum ath9k_rx_qtype qtype)
697 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
698 struct ath_hw *ah = sc->sc_ah;
699 struct ath_common *common = ath9k_hw_common(ah);
704 skb = skb_peek(&rx_edma->rx_fifo);
708 bf = SKB_CB_ATHBUF(skb);
711 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
712 common->rx_bufsize, DMA_FROM_DEVICE);
714 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
715 if (ret == -EINPROGRESS) {
716 /*let device gain the buffer again*/
717 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
718 common->rx_bufsize, DMA_FROM_DEVICE);
722 __skb_unlink(skb, &rx_edma->rx_fifo);
723 if (ret == -EINVAL) {
724 /* corrupt descriptor, skip this one and the following one */
725 list_add_tail(&bf->list, &sc->rx.rxbuf);
726 ath_rx_edma_buf_link(sc, qtype);
727 skb = skb_peek(&rx_edma->rx_fifo);
731 bf = SKB_CB_ATHBUF(skb);
734 __skb_unlink(skb, &rx_edma->rx_fifo);
735 list_add_tail(&bf->list, &sc->rx.rxbuf);
736 ath_rx_edma_buf_link(sc, qtype);
739 skb_queue_tail(&rx_edma->rx_buffers, skb);
744 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
745 struct ath_rx_status *rs,
746 enum ath9k_rx_qtype qtype)
748 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
752 while (ath_edma_get_buffers(sc, qtype));
753 skb = __skb_dequeue(&rx_edma->rx_buffers);
757 bf = SKB_CB_ATHBUF(skb);
758 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
762 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
763 struct ath_rx_status *rs)
765 struct ath_hw *ah = sc->sc_ah;
766 struct ath_common *common = ath9k_hw_common(ah);
771 if (list_empty(&sc->rx.rxbuf)) {
772 sc->rx.rxlink = NULL;
776 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
780 * Must provide the virtual address of the current
781 * descriptor, the physical address, and the virtual
782 * address of the next descriptor in the h/w chain.
783 * This allows the HAL to look ahead to see if the
784 * hardware is done with a descriptor by checking the
785 * done bit in the following descriptor and the address
786 * of the current descriptor the DMA engine is working
787 * on. All this is necessary because of our use of
788 * a self-linked list to avoid rx overruns.
790 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
791 if (ret == -EINPROGRESS) {
792 struct ath_rx_status trs;
794 struct ath_desc *tds;
796 memset(&trs, 0, sizeof(trs));
797 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
798 sc->rx.rxlink = NULL;
802 tbf = list_entry(bf->list.next, struct ath_buf, list);
805 * On some hardware the descriptor status words could
806 * get corrupted, including the done bit. Because of
807 * this, check if the next descriptor's done bit is
810 * If the next descriptor's done bit is set, the current
811 * descriptor has been corrupted. Force s/w to discard
812 * this descriptor and continue...
816 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
817 if (ret == -EINPROGRESS)
825 * Synchronize the DMA transfer with CPU before
826 * 1. accessing the frame
827 * 2. requeueing the same buffer to h/w
829 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
836 /* Assumes you've already done the endian to CPU conversion */
837 static bool ath9k_rx_accept(struct ath_common *common,
838 struct ieee80211_hdr *hdr,
839 struct ieee80211_rx_status *rxs,
840 struct ath_rx_status *rx_stats,
843 struct ath_hw *ah = common->ah;
845 u8 rx_status_len = ah->caps.rx_status_len;
847 fc = hdr->frame_control;
849 if (!rx_stats->rs_datalen)
852 * rs_status follows rs_datalen so if rs_datalen is too large
853 * we can take a hint that hardware corrupted it, so ignore
856 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
860 * rs_more indicates chained descriptors which can be used
861 * to link buffers together for a sort of scatter-gather
863 * reject the frame, we don't support scatter-gather yet and
864 * the frame is probably corrupt anyway
866 if (rx_stats->rs_more)
870 * The rx_stats->rs_status will not be set until the end of the
871 * chained descriptors so it can be ignored if rs_more is set. The
872 * rs_more will be false at the last element of the chained
875 if (rx_stats->rs_status != 0) {
876 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
877 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
878 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
881 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
882 *decrypt_error = true;
883 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
885 * The MIC error bit is only valid if the frame
886 * is not a control frame or fragment, and it was
887 * decrypted using a valid TKIP key.
889 if (!ieee80211_is_ctl(fc) &&
890 !ieee80211_has_morefrags(fc) &&
891 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
892 test_bit(rx_stats->rs_keyix, common->tkip_keymap))
893 rxs->flag |= RX_FLAG_MMIC_ERROR;
895 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
898 * Reject error frames with the exception of
899 * decryption and MIC failures. For monitor mode,
900 * we also ignore the CRC error.
902 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
903 if (rx_stats->rs_status &
904 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
908 if (rx_stats->rs_status &
909 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
917 static int ath9k_process_rate(struct ath_common *common,
918 struct ieee80211_hw *hw,
919 struct ath_rx_status *rx_stats,
920 struct ieee80211_rx_status *rxs)
922 struct ieee80211_supported_band *sband;
923 enum ieee80211_band band;
926 band = hw->conf.channel->band;
927 sband = hw->wiphy->bands[band];
929 if (rx_stats->rs_rate & 0x80) {
931 rxs->flag |= RX_FLAG_HT;
932 if (rx_stats->rs_flags & ATH9K_RX_2040)
933 rxs->flag |= RX_FLAG_40MHZ;
934 if (rx_stats->rs_flags & ATH9K_RX_GI)
935 rxs->flag |= RX_FLAG_SHORT_GI;
936 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
940 for (i = 0; i < sband->n_bitrates; i++) {
941 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
945 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
946 rxs->flag |= RX_FLAG_SHORTPRE;
953 * No valid hardware bitrate found -- we should not get here
954 * because hardware has already validated this frame as OK.
956 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
957 "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
962 static void ath9k_process_rssi(struct ath_common *common,
963 struct ieee80211_hw *hw,
964 struct ieee80211_hdr *hdr,
965 struct ath_rx_status *rx_stats)
967 struct ath_hw *ah = common->ah;
968 struct ieee80211_sta *sta;
970 int last_rssi = ATH_RSSI_DUMMY_MARKER;
973 fc = hdr->frame_control;
977 * XXX: use ieee80211_find_sta! This requires quite a bit of work
978 * under the current ath9k virtual wiphy implementation as we have
979 * no way of tying a vif to wiphy. Typically vifs are attached to
980 * at least one sdata of a wiphy on mac80211 but with ath9k virtual
981 * wiphy you'd have to iterate over every wiphy and each sdata.
983 if (is_multicast_ether_addr(hdr->addr1))
984 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, NULL);
986 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, hdr->addr1);
989 an = (struct ath_node *) sta->drv_priv;
990 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
991 !rx_stats->rs_moreaggr)
992 ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
993 last_rssi = an->last_rssi;
997 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
998 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
999 ATH_RSSI_EP_MULTIPLIER);
1000 if (rx_stats->rs_rssi < 0)
1001 rx_stats->rs_rssi = 0;
1003 /* Update Beacon RSSI, this is used by ANI. */
1004 if (ieee80211_is_beacon(fc))
1005 ah->stats.avgbrssi = rx_stats->rs_rssi;
1009 * For Decrypt or Demic errors, we only mark packet status here and always push
1010 * up the frame up to let mac80211 handle the actual error case, be it no
1011 * decryption key or real decryption error. This let us keep statistics there.
1013 static int ath9k_rx_skb_preprocess(struct ath_common *common,
1014 struct ieee80211_hw *hw,
1015 struct ieee80211_hdr *hdr,
1016 struct ath_rx_status *rx_stats,
1017 struct ieee80211_rx_status *rx_status,
1018 bool *decrypt_error)
1020 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1023 * everything but the rate is checked here, the rate check is done
1024 * separately to avoid doing two lookups for a rate for each frame.
1026 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1029 ath9k_process_rssi(common, hw, hdr, rx_stats);
1031 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1034 rx_status->band = hw->conf.channel->band;
1035 rx_status->freq = hw->conf.channel->center_freq;
1036 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1037 rx_status->antenna = rx_stats->rs_antenna;
1038 rx_status->flag |= RX_FLAG_TSFT;
1043 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1044 struct sk_buff *skb,
1045 struct ath_rx_status *rx_stats,
1046 struct ieee80211_rx_status *rxs,
1049 struct ath_hw *ah = common->ah;
1050 struct ieee80211_hdr *hdr;
1051 int hdrlen, padpos, padsize;
1055 /* see if any padding is done by the hw and remove it */
1056 hdr = (struct ieee80211_hdr *) skb->data;
1057 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1058 fc = hdr->frame_control;
1059 padpos = ath9k_cmn_padpos(hdr->frame_control);
1061 /* The MAC header is padded to have 32-bit boundary if the
1062 * packet payload is non-zero. The general calculation for
1063 * padsize would take into account odd header lengths:
1064 * padsize = (4 - padpos % 4) % 4; However, since only
1065 * even-length headers are used, padding can only be 0 or 2
1066 * bytes and we can optimize this a bit. In addition, we must
1067 * not try to remove padding from short control frames that do
1068 * not have payload. */
1069 padsize = padpos & 3;
1070 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1071 memmove(skb->data + padsize, skb->data, padpos);
1072 skb_pull(skb, padsize);
1075 keyix = rx_stats->rs_keyix;
1077 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1078 ieee80211_has_protected(fc)) {
1079 rxs->flag |= RX_FLAG_DECRYPTED;
1080 } else if (ieee80211_has_protected(fc)
1081 && !decrypt_error && skb->len >= hdrlen + 4) {
1082 keyix = skb->data[hdrlen + 3] >> 6;
1084 if (test_bit(keyix, common->keymap))
1085 rxs->flag |= RX_FLAG_DECRYPTED;
1087 if (ah->sw_mgmt_crypto &&
1088 (rxs->flag & RX_FLAG_DECRYPTED) &&
1089 ieee80211_is_mgmt(fc))
1090 /* Use software decrypt for management frames. */
1091 rxs->flag &= ~RX_FLAG_DECRYPTED;
1094 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1095 struct ath_hw_antcomb_conf ant_conf,
1098 antcomb->quick_scan_cnt = 0;
1100 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1101 antcomb->rssi_lna2 = main_rssi_avg;
1102 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1103 antcomb->rssi_lna1 = main_rssi_avg;
1105 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1106 case (0x10): /* LNA2 A-B */
1107 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1108 antcomb->first_quick_scan_conf =
1109 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1110 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1112 case (0x20): /* LNA1 A-B */
1113 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1114 antcomb->first_quick_scan_conf =
1115 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1116 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1118 case (0x21): /* LNA1 LNA2 */
1119 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1120 antcomb->first_quick_scan_conf =
1121 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1122 antcomb->second_quick_scan_conf =
1123 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1125 case (0x12): /* LNA2 LNA1 */
1126 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1127 antcomb->first_quick_scan_conf =
1128 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1129 antcomb->second_quick_scan_conf =
1130 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1132 case (0x13): /* LNA2 A+B */
1133 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1134 antcomb->first_quick_scan_conf =
1135 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1136 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1138 case (0x23): /* LNA1 A+B */
1139 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1140 antcomb->first_quick_scan_conf =
1141 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1142 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1149 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1150 struct ath_hw_antcomb_conf *div_ant_conf,
1151 int main_rssi_avg, int alt_rssi_avg,
1155 switch (antcomb->quick_scan_cnt) {
1157 /* set alt to main, and alt to first conf */
1158 div_ant_conf->main_lna_conf = antcomb->main_conf;
1159 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1162 /* set alt to main, and alt to first conf */
1163 div_ant_conf->main_lna_conf = antcomb->main_conf;
1164 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1165 antcomb->rssi_first = main_rssi_avg;
1166 antcomb->rssi_second = alt_rssi_avg;
1168 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1170 if (ath_is_alt_ant_ratio_better(alt_ratio,
1171 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1172 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1173 main_rssi_avg, alt_rssi_avg,
1174 antcomb->total_pkt_count))
1175 antcomb->first_ratio = true;
1177 antcomb->first_ratio = false;
1178 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1179 if (ath_is_alt_ant_ratio_better(alt_ratio,
1180 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1181 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1182 main_rssi_avg, alt_rssi_avg,
1183 antcomb->total_pkt_count))
1184 antcomb->first_ratio = true;
1186 antcomb->first_ratio = false;
1188 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1189 (alt_rssi_avg > main_rssi_avg +
1190 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1191 (alt_rssi_avg > main_rssi_avg)) &&
1192 (antcomb->total_pkt_count > 50))
1193 antcomb->first_ratio = true;
1195 antcomb->first_ratio = false;
1199 antcomb->alt_good = false;
1200 antcomb->scan_not_start = false;
1201 antcomb->scan = false;
1202 antcomb->rssi_first = main_rssi_avg;
1203 antcomb->rssi_third = alt_rssi_avg;
1205 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1206 antcomb->rssi_lna1 = alt_rssi_avg;
1207 else if (antcomb->second_quick_scan_conf ==
1208 ATH_ANT_DIV_COMB_LNA2)
1209 antcomb->rssi_lna2 = alt_rssi_avg;
1210 else if (antcomb->second_quick_scan_conf ==
1211 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1212 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1213 antcomb->rssi_lna2 = main_rssi_avg;
1214 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1215 antcomb->rssi_lna1 = main_rssi_avg;
1218 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1219 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1220 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1222 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1224 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1225 if (ath_is_alt_ant_ratio_better(alt_ratio,
1226 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1227 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1228 main_rssi_avg, alt_rssi_avg,
1229 antcomb->total_pkt_count))
1230 antcomb->second_ratio = true;
1232 antcomb->second_ratio = false;
1233 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1234 if (ath_is_alt_ant_ratio_better(alt_ratio,
1235 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1236 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1237 main_rssi_avg, alt_rssi_avg,
1238 antcomb->total_pkt_count))
1239 antcomb->second_ratio = true;
1241 antcomb->second_ratio = false;
1243 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1244 (alt_rssi_avg > main_rssi_avg +
1245 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1246 (alt_rssi_avg > main_rssi_avg)) &&
1247 (antcomb->total_pkt_count > 50))
1248 antcomb->second_ratio = true;
1250 antcomb->second_ratio = false;
1253 /* set alt to the conf with maximun ratio */
1254 if (antcomb->first_ratio && antcomb->second_ratio) {
1255 if (antcomb->rssi_second > antcomb->rssi_third) {
1257 if ((antcomb->first_quick_scan_conf ==
1258 ATH_ANT_DIV_COMB_LNA1) ||
1259 (antcomb->first_quick_scan_conf ==
1260 ATH_ANT_DIV_COMB_LNA2))
1261 /* Set alt LNA1 or LNA2*/
1262 if (div_ant_conf->main_lna_conf ==
1263 ATH_ANT_DIV_COMB_LNA2)
1264 div_ant_conf->alt_lna_conf =
1265 ATH_ANT_DIV_COMB_LNA1;
1267 div_ant_conf->alt_lna_conf =
1268 ATH_ANT_DIV_COMB_LNA2;
1270 /* Set alt to A+B or A-B */
1271 div_ant_conf->alt_lna_conf =
1272 antcomb->first_quick_scan_conf;
1273 } else if ((antcomb->second_quick_scan_conf ==
1274 ATH_ANT_DIV_COMB_LNA1) ||
1275 (antcomb->second_quick_scan_conf ==
1276 ATH_ANT_DIV_COMB_LNA2)) {
1277 /* Set alt LNA1 or LNA2 */
1278 if (div_ant_conf->main_lna_conf ==
1279 ATH_ANT_DIV_COMB_LNA2)
1280 div_ant_conf->alt_lna_conf =
1281 ATH_ANT_DIV_COMB_LNA1;
1283 div_ant_conf->alt_lna_conf =
1284 ATH_ANT_DIV_COMB_LNA2;
1286 /* Set alt to A+B or A-B */
1287 div_ant_conf->alt_lna_conf =
1288 antcomb->second_quick_scan_conf;
1290 } else if (antcomb->first_ratio) {
1292 if ((antcomb->first_quick_scan_conf ==
1293 ATH_ANT_DIV_COMB_LNA1) ||
1294 (antcomb->first_quick_scan_conf ==
1295 ATH_ANT_DIV_COMB_LNA2))
1296 /* Set alt LNA1 or LNA2 */
1297 if (div_ant_conf->main_lna_conf ==
1298 ATH_ANT_DIV_COMB_LNA2)
1299 div_ant_conf->alt_lna_conf =
1300 ATH_ANT_DIV_COMB_LNA1;
1302 div_ant_conf->alt_lna_conf =
1303 ATH_ANT_DIV_COMB_LNA2;
1305 /* Set alt to A+B or A-B */
1306 div_ant_conf->alt_lna_conf =
1307 antcomb->first_quick_scan_conf;
1308 } else if (antcomb->second_ratio) {
1310 if ((antcomb->second_quick_scan_conf ==
1311 ATH_ANT_DIV_COMB_LNA1) ||
1312 (antcomb->second_quick_scan_conf ==
1313 ATH_ANT_DIV_COMB_LNA2))
1314 /* Set alt LNA1 or LNA2 */
1315 if (div_ant_conf->main_lna_conf ==
1316 ATH_ANT_DIV_COMB_LNA2)
1317 div_ant_conf->alt_lna_conf =
1318 ATH_ANT_DIV_COMB_LNA1;
1320 div_ant_conf->alt_lna_conf =
1321 ATH_ANT_DIV_COMB_LNA2;
1323 /* Set alt to A+B or A-B */
1324 div_ant_conf->alt_lna_conf =
1325 antcomb->second_quick_scan_conf;
1327 /* main is largest */
1328 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1329 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1330 /* Set alt LNA1 or LNA2 */
1331 if (div_ant_conf->main_lna_conf ==
1332 ATH_ANT_DIV_COMB_LNA2)
1333 div_ant_conf->alt_lna_conf =
1334 ATH_ANT_DIV_COMB_LNA1;
1336 div_ant_conf->alt_lna_conf =
1337 ATH_ANT_DIV_COMB_LNA2;
1339 /* Set alt to A+B or A-B */
1340 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1348 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1350 /* Adjust the fast_div_bias based on main and alt lna conf */
1351 switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1352 case (0x01): /* A-B LNA2 */
1353 ant_conf->fast_div_bias = 0x3b;
1355 case (0x02): /* A-B LNA1 */
1356 ant_conf->fast_div_bias = 0x3d;
1358 case (0x03): /* A-B A+B */
1359 ant_conf->fast_div_bias = 0x1;
1361 case (0x10): /* LNA2 A-B */
1362 ant_conf->fast_div_bias = 0x7;
1364 case (0x12): /* LNA2 LNA1 */
1365 ant_conf->fast_div_bias = 0x2;
1367 case (0x13): /* LNA2 A+B */
1368 ant_conf->fast_div_bias = 0x7;
1370 case (0x20): /* LNA1 A-B */
1371 ant_conf->fast_div_bias = 0x6;
1373 case (0x21): /* LNA1 LNA2 */
1374 ant_conf->fast_div_bias = 0x0;
1376 case (0x23): /* LNA1 A+B */
1377 ant_conf->fast_div_bias = 0x6;
1379 case (0x30): /* A+B A-B */
1380 ant_conf->fast_div_bias = 0x1;
1382 case (0x31): /* A+B LNA2 */
1383 ant_conf->fast_div_bias = 0x3b;
1385 case (0x32): /* A+B LNA1 */
1386 ant_conf->fast_div_bias = 0x3d;
1393 /* Antenna diversity and combining */
1394 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1396 struct ath_hw_antcomb_conf div_ant_conf;
1397 struct ath_ant_comb *antcomb = &sc->ant_comb;
1398 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1399 int curr_main_set, curr_bias;
1400 int main_rssi = rs->rs_rssi_ctl0;
1401 int alt_rssi = rs->rs_rssi_ctl1;
1402 int rx_ant_conf, main_ant_conf;
1403 bool short_scan = false;
1405 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1407 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1410 /* Record packet only when alt_rssi is positive */
1412 antcomb->total_pkt_count++;
1413 antcomb->main_total_rssi += main_rssi;
1414 antcomb->alt_total_rssi += alt_rssi;
1415 if (main_ant_conf == rx_ant_conf)
1416 antcomb->main_recv_cnt++;
1418 antcomb->alt_recv_cnt++;
1421 /* Short scan check */
1422 if (antcomb->scan && antcomb->alt_good) {
1423 if (time_after(jiffies, antcomb->scan_start_time +
1424 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1427 if (antcomb->total_pkt_count ==
1428 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1429 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1430 antcomb->total_pkt_count);
1431 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1436 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1437 rs->rs_moreaggr) && !short_scan)
1440 if (antcomb->total_pkt_count) {
1441 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1442 antcomb->total_pkt_count);
1443 main_rssi_avg = (antcomb->main_total_rssi /
1444 antcomb->total_pkt_count);
1445 alt_rssi_avg = (antcomb->alt_total_rssi /
1446 antcomb->total_pkt_count);
1450 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1451 curr_alt_set = div_ant_conf.alt_lna_conf;
1452 curr_main_set = div_ant_conf.main_lna_conf;
1453 curr_bias = div_ant_conf.fast_div_bias;
1457 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1458 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1459 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1461 antcomb->alt_good = true;
1463 antcomb->alt_good = false;
1467 antcomb->scan = true;
1468 antcomb->scan_not_start = true;
1471 if (!antcomb->scan) {
1472 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1473 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1474 /* Switch main and alt LNA */
1475 div_ant_conf.main_lna_conf =
1476 ATH_ANT_DIV_COMB_LNA2;
1477 div_ant_conf.alt_lna_conf =
1478 ATH_ANT_DIV_COMB_LNA1;
1479 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1480 div_ant_conf.main_lna_conf =
1481 ATH_ANT_DIV_COMB_LNA1;
1482 div_ant_conf.alt_lna_conf =
1483 ATH_ANT_DIV_COMB_LNA2;
1487 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1488 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1489 /* Set alt to another LNA */
1490 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1491 div_ant_conf.alt_lna_conf =
1492 ATH_ANT_DIV_COMB_LNA1;
1493 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1494 div_ant_conf.alt_lna_conf =
1495 ATH_ANT_DIV_COMB_LNA2;
1500 if ((alt_rssi_avg < (main_rssi_avg +
1501 ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1505 if (!antcomb->scan_not_start) {
1506 switch (curr_alt_set) {
1507 case ATH_ANT_DIV_COMB_LNA2:
1508 antcomb->rssi_lna2 = alt_rssi_avg;
1509 antcomb->rssi_lna1 = main_rssi_avg;
1510 antcomb->scan = true;
1512 div_ant_conf.main_lna_conf =
1513 ATH_ANT_DIV_COMB_LNA1;
1514 div_ant_conf.alt_lna_conf =
1515 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1517 case ATH_ANT_DIV_COMB_LNA1:
1518 antcomb->rssi_lna1 = alt_rssi_avg;
1519 antcomb->rssi_lna2 = main_rssi_avg;
1520 antcomb->scan = true;
1522 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1523 div_ant_conf.alt_lna_conf =
1524 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1526 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1527 antcomb->rssi_add = alt_rssi_avg;
1528 antcomb->scan = true;
1530 div_ant_conf.alt_lna_conf =
1531 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1533 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1534 antcomb->rssi_sub = alt_rssi_avg;
1535 antcomb->scan = false;
1536 if (antcomb->rssi_lna2 >
1537 (antcomb->rssi_lna1 +
1538 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1539 /* use LNA2 as main LNA */
1540 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1541 (antcomb->rssi_add > antcomb->rssi_sub)) {
1543 div_ant_conf.main_lna_conf =
1544 ATH_ANT_DIV_COMB_LNA2;
1545 div_ant_conf.alt_lna_conf =
1546 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1547 } else if (antcomb->rssi_sub >
1548 antcomb->rssi_lna1) {
1550 div_ant_conf.main_lna_conf =
1551 ATH_ANT_DIV_COMB_LNA2;
1552 div_ant_conf.alt_lna_conf =
1553 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1556 div_ant_conf.main_lna_conf =
1557 ATH_ANT_DIV_COMB_LNA2;
1558 div_ant_conf.alt_lna_conf =
1559 ATH_ANT_DIV_COMB_LNA1;
1562 /* use LNA1 as main LNA */
1563 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1564 (antcomb->rssi_add > antcomb->rssi_sub)) {
1566 div_ant_conf.main_lna_conf =
1567 ATH_ANT_DIV_COMB_LNA1;
1568 div_ant_conf.alt_lna_conf =
1569 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1570 } else if (antcomb->rssi_sub >
1571 antcomb->rssi_lna1) {
1573 div_ant_conf.main_lna_conf =
1574 ATH_ANT_DIV_COMB_LNA1;
1575 div_ant_conf.alt_lna_conf =
1576 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1579 div_ant_conf.main_lna_conf =
1580 ATH_ANT_DIV_COMB_LNA1;
1581 div_ant_conf.alt_lna_conf =
1582 ATH_ANT_DIV_COMB_LNA2;
1590 if (!antcomb->alt_good) {
1591 antcomb->scan_not_start = false;
1592 /* Set alt to another LNA */
1593 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1594 div_ant_conf.main_lna_conf =
1595 ATH_ANT_DIV_COMB_LNA2;
1596 div_ant_conf.alt_lna_conf =
1597 ATH_ANT_DIV_COMB_LNA1;
1598 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1599 div_ant_conf.main_lna_conf =
1600 ATH_ANT_DIV_COMB_LNA1;
1601 div_ant_conf.alt_lna_conf =
1602 ATH_ANT_DIV_COMB_LNA2;
1608 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1609 main_rssi_avg, alt_rssi_avg,
1612 antcomb->quick_scan_cnt++;
1615 ath_ant_div_conf_fast_divbias(&div_ant_conf);
1617 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1619 antcomb->scan_start_time = jiffies;
1620 antcomb->total_pkt_count = 0;
1621 antcomb->main_total_rssi = 0;
1622 antcomb->alt_total_rssi = 0;
1623 antcomb->main_recv_cnt = 0;
1624 antcomb->alt_recv_cnt = 0;
1627 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1630 struct sk_buff *skb = NULL, *requeue_skb;
1631 struct ieee80211_rx_status *rxs;
1632 struct ath_hw *ah = sc->sc_ah;
1633 struct ath_common *common = ath9k_hw_common(ah);
1635 * The hw can techncically differ from common->hw when using ath9k
1636 * virtual wiphy so to account for that we iterate over the active
1637 * wiphys and find the appropriate wiphy and therefore hw.
1639 struct ieee80211_hw *hw = NULL;
1640 struct ieee80211_hdr *hdr;
1642 bool decrypt_error = false;
1643 struct ath_rx_status rs;
1644 enum ath9k_rx_qtype qtype;
1645 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1647 u8 rx_status_len = ah->caps.rx_status_len;
1650 unsigned long flags;
1653 dma_type = DMA_BIDIRECTIONAL;
1655 dma_type = DMA_FROM_DEVICE;
1657 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1658 spin_lock_bh(&sc->rx.rxbuflock);
1660 tsf = ath9k_hw_gettsf64(ah);
1661 tsf_lower = tsf & 0xffffffff;
1664 /* If handling rx interrupt and flush is in progress => exit */
1665 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1668 memset(&rs, 0, sizeof(rs));
1670 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1672 bf = ath_get_next_rx_buf(sc, &rs);
1681 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1682 rxs = IEEE80211_SKB_RXCB(skb);
1684 hw = ath_get_virt_hw(sc, hdr);
1686 ath_debug_stat_rx(sc, &rs);
1689 * If we're asked to flush receive queue, directly
1690 * chain it back at the queue without processing it.
1695 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1696 rxs, &decrypt_error);
1700 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1701 if (rs.rs_tstamp > tsf_lower &&
1702 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1703 rxs->mactime -= 0x100000000ULL;
1705 if (rs.rs_tstamp < tsf_lower &&
1706 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1707 rxs->mactime += 0x100000000ULL;
1709 /* Ensure we always have an skb to requeue once we are done
1710 * processing the current buffer's skb */
1711 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1713 /* If there is no memory we ignore the current RX'd frame,
1714 * tell hardware it can give us a new frame using the old
1715 * skb and put it at the tail of the sc->rx.rxbuf list for
1720 /* Unmap the frame */
1721 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1725 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1726 if (ah->caps.rx_status_len)
1727 skb_pull(skb, ah->caps.rx_status_len);
1729 ath9k_rx_skb_postprocess(common, skb, &rs,
1730 rxs, decrypt_error);
1732 /* We will now give hardware our shiny new allocated skb */
1733 bf->bf_mpdu = requeue_skb;
1734 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1737 if (unlikely(dma_mapping_error(sc->dev,
1738 bf->bf_buf_addr))) {
1739 dev_kfree_skb_any(requeue_skb);
1741 bf->bf_buf_addr = 0;
1742 ath_print(common, ATH_DBG_FATAL,
1743 "dma_mapping_error() on RX\n");
1744 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1749 * change the default rx antenna if rx diversity chooses the
1750 * other antenna 3 times in a row.
1752 if (sc->rx.defant != rs.rs_antenna) {
1753 if (++sc->rx.rxotherant >= 3)
1754 ath_setdefantenna(sc, rs.rs_antenna);
1756 sc->rx.rxotherant = 0;
1759 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1760 if (unlikely(ath9k_check_auto_sleep(sc) ||
1761 (sc->ps_flags & (PS_WAIT_FOR_BEACON |
1763 PS_WAIT_FOR_PSPOLL_DATA))))
1765 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1767 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1768 ath_ant_comb_scan(sc, &rs);
1770 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1774 list_add_tail(&bf->list, &sc->rx.rxbuf);
1775 ath_rx_edma_buf_link(sc, qtype);
1777 list_move_tail(&bf->list, &sc->rx.rxbuf);
1778 ath_rx_buf_link(sc, bf);
1782 spin_unlock_bh(&sc->rx.rxbuflock);