i2c-omap: Double clear of ARDY status in IRQ handler
authorRichard woodruff <r-woodruff2@ti.com>
Wed, 16 Feb 2011 04:54:16 +0000 (10:24 +0530)
committerBen Dooks <ben-linux@fluff.org>
Wed, 23 Feb 2011 00:42:36 +0000 (00:42 +0000)
commitcb527ede1bf6ff2008a025606f25344b8ed7b4ac
treedd7fa2c6496097b5ff130718957d1ca5aa9f4d17
parentf72487e7a1827f5e95425b80ec4fcc4f928329e8
i2c-omap: Double clear of ARDY status in IRQ handler

This errata occurs when the ARDY interrupt generation is enabled.
At the begining of every new transaction the ARDY interrupt is cleared.

On continuous i2c transactions where after clearing the ARDY bit from
I2C_STAT register (clearing the interrupt), the IRQ line is reasserted and the
I2C_STAT[ARDY] bit set again on 1. In fact, the ARDY status bit is not cleared
at the write access to I2C_STAT[ARDY] and only the IRQ line is deasserted and
then reasserted. This is not captured in the usual errata documents.

The workaround is to have a double clear of ARDY status in irq handler.

Signed-off-by: Richard woodruff <r-woodruff2@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
drivers/i2c/busses/i2c-omap.c