mtip32xx: Fix ERO and NoSnoop values in PCIe upstream on AMD systems
authorAsai Thambi S P <asamymuthupa@micron.com>
Fri, 14 Mar 2014 01:45:15 +0000 (18:45 -0700)
committerJens Axboe <axboe@fb.com>
Wed, 23 Apr 2014 01:48:52 +0000 (19:48 -0600)
commitd1e714db8129a1d3670e449b87719c78e2c76f9f
tree34ed981357620ab4d648edc4d680d85f079e2a51
parentaf5ded8ccf21627f9614afc03b356712666ed225
mtip32xx: Fix ERO and NoSnoop values in PCIe upstream on AMD systems

A hardware quirk in P320h/P420m interfere with PCIe transactions on some
AMD chipsets, making P320h/P420m unusable. This workaround is to disable
ERO and NoSnoop bits in the parent and root complex for normal
functioning of these devices

NOTE: This workaround is specific to AMD chipset with a PCIe upstream
device with device id 0x5aXX

Signed-off-by: Asai Thambi S P <asamymuthupa@micron.com>
Signed-off-by: Sam Bradshaw <sbradshaw@micron.com>
Cc: stable@kernel.org
Signed-off-by: Jens Axboe <axboe@fb.com>
drivers/block/mtip32xx/mtip32xx.c