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ARM: vexpress/dcscb: fix cache disabling sequences
authorNicolas Pitre <nicolas.pitre@linaro.org>
Wed, 17 Jul 2013 00:59:53 +0000 (20:59 -0400)
committerNicolas Pitre <nicolas.pitre@linaro.org>
Mon, 22 Jul 2013 16:26:09 +0000 (12:26 -0400)
commite8f9bb1bd6bb93fff773345cc54c42585e0e3ece
tree730257640b01d6b83b3a37d0c4961e0189faaddctree | snapshot
parent3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4bcommit | diff
ARM: vexpress/dcscb: fix cache disabling sequences

Unlike real A15/A7's, the RTSM simulation doesn't appear to hit the
cache when the CTRL.C bit is cleared.  Let's ensure there is no memory
access within the disable and flush cache sequence, including to the
stack.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
arch/arm/mach-vexpress/dcscb.c diff | blob | history
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