From 019f162a100e7a98f0b92655c895df0ddbfde0ff Mon Sep 17 00:00:00 2001 From: =?utf8?q?=E9=BB=84=E6=B6=9B?= Date: Wed, 23 Jan 2013 23:09:20 +0800 Subject: [PATCH] rk3188: fix cpu aix init --- arch/arm/mach-rk30/common.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rk30/common.c b/arch/arm/mach-rk30/common.c index 2822b581af15..8c381862348a 100755 --- a/arch/arm/mach-rk30/common.c +++ b/arch/arm/mach-rk30/common.c @@ -22,11 +22,17 @@ static void __init rk30_cpu_axi_init(void) { -#ifndef CONFIG_ARCH_RK3188 +#ifdef CONFIG_ARCH_RK3188 + writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x1008); // dmac1 + writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x2008); // cpu0 + writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x2088); // cpu1r + writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x2108); // cpu1w +#else writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x0088); // cpu0 writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x0108); // dmac1 writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x0188); // cpu1r writel_relaxed(0x0, RK30_CPU_AXI_BUS_BASE + 0x0388); // cpu1w +#endif #ifdef CONFIG_RK29_VMAC writel_relaxed(0xa, RK30_CPU_AXI_BUS_BASE + 0x4008); // peri #else @@ -44,7 +50,6 @@ static void __init rk30_cpu_axi_init(void) #endif writel_relaxed(0x3f, RK30_CPU_AXI_BUS_BASE + 0x0014); // memory scheduler read latency dsb(); -#endif } static void __init rk30_io_drive_strength_init(void) -- 2.34.1