From 022ed327bd455348dbe0fbe0915219cb8b4cb6e1 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 15 May 2005 19:54:37 +0000 Subject: [PATCH] Fix andrews changes to fit in 80 columns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22064 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC64ISelPattern.cpp | 18 +++++++++++------ lib/Target/PowerPC/PPCISelPattern.cpp | 27 ++++++++++++++++--------- 2 files changed, 30 insertions(+), 15 deletions(-) diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp index 41138cf7ef0..1d528a9a5b9 100644 --- a/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -195,7 +195,8 @@ PPC64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); FIN = DAG.getNode(ISD::ADD, MVT::i64, FIN, DAG.getConstant(SubregOffset, MVT::i64)); - argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, + DAG.getSrcValue(NULL)); } // Every 4 bytes of argument space consumes one of the GPRs available for @@ -305,7 +306,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, --GPR_remaining; } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL))); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL))); } ArgOffset += 8; break; @@ -316,11 +318,13 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, --FPR_remaining; if (isVarArg) { SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL)); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL)); MemOps.push_back(Store); // Float varargs are always shadowed in available integer registers if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(MVT::i64, Store, PtrOff, + DAG.getSrcValue(NULL)); MemOps.push_back(Load); args_to_use.push_back(Load); --GPR_remaining; @@ -335,7 +339,8 @@ PPC64TargetLowering::LowerCallTo(SDOperand Chain, } } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL))); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL))); } ArgOffset += 8; break; @@ -371,7 +376,8 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, MVT::ValueType ArgVT = getValueType(ArgTy); SDOperand Result; if (!isVANext) { - Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL)); + Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, + DAG.getSrcValue(NULL)); } else { Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, DAG.getConstant(8, VAList.getValueType())); diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 9150306d814..410c62e661a 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -182,7 +182,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { } else { int FI = MFI->CreateFixedObject(4, ArgOffset+4); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); - argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, + DAG.getSrcValue(NULL)); } // Build the outgoing arg thingy argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); @@ -217,7 +218,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, DAG.getConstant(SubregOffset, MVT::i32)); - argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL)); + argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, + DAG.getSrcValue(NULL)); } // Every 4 bytes of argument space consumes one of the GPRs available for @@ -362,7 +364,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, --GPR_remaining; } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL))); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL))); } ArgOffset += 4; break; @@ -388,7 +391,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, } } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL))); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL))); } ArgOffset += 8; break; @@ -399,11 +403,13 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, --FPR_remaining; if (isVarArg) { SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL)); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL)); MemOps.push_back(Store); // Float varargs are always shadowed in available integer registers if (GPR_remaining > 0) { - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); MemOps.push_back(Load); args_to_use.push_back(Load); --GPR_remaining; @@ -411,7 +417,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, if (GPR_remaining > 0 && MVT::f64 == ArgVT) { SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); - SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, DAG.getSrcValue(NULL)); + SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, + DAG.getSrcValue(NULL)); MemOps.push_back(Load); args_to_use.push_back(Load); --GPR_remaining; @@ -431,7 +438,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain, } } else { MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, - Args[i].first, PtrOff, DAG.getSrcValue(NULL))); + Args[i].first, PtrOff, + DAG.getSrcValue(NULL))); } ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; break; @@ -467,7 +475,8 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList, MVT::ValueType ArgVT = getValueType(ArgTy); SDOperand Result; if (!isVANext) { - Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, DAG.getSrcValue(NULL)); + Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList, + DAG.getSrcValue(NULL)); } else { unsigned Amt; if (ArgVT == MVT::i32 || ArgVT == MVT::f32) -- 2.34.1