From 0301bc54ad23c9dff0370dffaf6eb3eabba42cc4 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 15 Nov 2012 21:17:13 +0000 Subject: [PATCH] [mips] Add predicate HasFPIdx for floating-point indexed load instruction support and use it in place of HasMips32r2Or64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips.td | 7 +++++-- lib/Target/Mips/MipsISelDAGToDAG.cpp | 4 ++-- lib/Target/Mips/MipsInstrFPU.td | 2 +- lib/Target/Mips/MipsInstrInfo.td | 4 ++-- lib/Target/Mips/MipsSubtarget.cpp | 4 ++-- lib/Target/Mips/MipsSubtarget.h | 6 ++++-- 6 files changed, 16 insertions(+), 11 deletions(-) diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 90c01d5de0a..31194ae6105 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -60,16 +60,19 @@ def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", "Enable 'byte/half swap' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; +def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", + "Enable 'FP indexed load/store' instructions.">; def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", "Mips32 ISA Support", [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", - [FeatureMips32, FeatureSEInReg, FeatureSwap]>; + [FeatureMips32, FeatureSEInReg, FeatureSwap, + FeatureFPIdx]>; def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", "Mips64", "Mips64 ISA Support", [FeatureGP64Bit, FeatureFP64Bit, - FeatureMips32]>; + FeatureMips32, FeatureFPIdx]>; def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", "Mips64r2", "Mips64r2 ISA Support", [FeatureMips64, FeatureMips32r2]>; diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index c5fca7f4b27..acfbad235f3 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -390,7 +390,7 @@ SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) { if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && - Subtarget.hasMips32r2Or64()) + Subtarget.hasFPIdx()) return false; } @@ -500,7 +500,7 @@ bool MipsDAGToDAGISel::SelectAddr16( if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) && - Subtarget.hasMips32r2Or64()) + Subtarget.hasFPIdx()) return false; } Base = Addr; diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 33ee0206894..750b700aeea 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -282,7 +282,7 @@ let Predicates = [NotN64, NotMips64, HasStandardEncoding] in { } // Indexed loads and stores. -let Predicates = [HasMips32r2Or64, HasStandardEncoding] in { +let Predicates = [HasFPIdx, HasStandardEncoding] in { def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load>; def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store>; } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index f16b5f9ee7f..91970662890 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -148,14 +148,14 @@ def HasSwap : Predicate<"Subtarget.hasSwap()">, AssemblerPredicate<"FeatureSwap">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">, AssemblerPredicate<"FeatureCondMov">; +def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, + AssemblerPredicate<"FeatureFPIdx">; def HasMips32 : Predicate<"Subtarget.hasMips32()">, AssemblerPredicate<"FeatureMips32">; def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, AssemblerPredicate<"FeatureMips32r2">; def HasMips64 : Predicate<"Subtarget.hasMips64()">, AssemblerPredicate<"FeatureMips64">; -def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, - AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; def NotMips64 : Predicate<"!Subtarget.hasMips64()">, AssemblerPredicate<"!FeatureMips64">; def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 930af4dda15..a7436ad8606 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -31,8 +31,8 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, MipsArchVersion(Mips32), MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), - HasMinMax(false), HasSwap(false), HasBitCount(false), InMips16Mode(false), - HasDSP(false), HasDSPR2(false), IsAndroid(false) + HasMinMax(false), HasSwap(false), HasBitCount(false), HasFPIdx(false), + InMips16Mode(false), HasDSP(false), HasDSPR2(false), IsAndroid(false) { std::string CPUName = CPU; if (CPUName.empty()) diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index ff69237ec2b..ff32219c7d6 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -89,6 +89,9 @@ protected: // HasBitCount - Count leading '1' and '0' bits. bool HasBitCount; + // HasFPIdx -- Floating point indexed load/store instructions. + bool HasFPIdx; + // InMips16 -- can process Mips16 instructions bool InMips16Mode; @@ -127,8 +130,6 @@ public: bool hasMips64() const { return MipsArchVersion >= Mips64; } bool hasMips64r2() const { return MipsArchVersion == Mips64r2; } - bool hasMips32r2Or64() const { return hasMips32r2() || hasMips64(); } - bool isLittle() const { return IsLittle; } bool isFP64bit() const { return IsFP64bit; } bool isGP64bit() const { return IsGP64bit; } @@ -152,6 +153,7 @@ public: bool hasMinMax() const { return HasMinMax; } bool hasSwap() const { return HasSwap; } bool hasBitCount() const { return HasBitCount; } + bool hasFPIdx() const { return HasFPIdx; } }; } // End llvm namespace -- 2.34.1