From 03494d7c8ff981a7466da89fd6798313b2fb222e Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 13 Jul 2007 23:55:50 +0000
Subject: [PATCH] Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/SparcRegisterInfo.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index 11251e92581..8e2f4444b85 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> {
   let Num = num;
 }
 // Rd - Slots in the FP register file for 64-bit floating-point values.
-class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
+class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
   let Num = num;
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }
 
 // Integer registers
-- 
2.34.1