From 04b24f19e583fd82603cf80eddeded9ba25806e2 Mon Sep 17 00:00:00 2001 From: chenyifu Date: Mon, 2 Mar 2015 17:03:57 +0800 Subject: [PATCH] rk3368 mipi: fix the phase between the mipi clock and mipi data The mipi screen may be no-display in rk3368 when the mipi rate higher than 900M, so we need to fix the phase between the clock and data. Signed-off-by: chenyifu --- drivers/video/rockchip/transmitter/rk32_mipi_dsi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c index 385f0c915435..f3d1d26e18aa 100755 --- a/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c +++ b/drivers/video/rockchip/transmitter/rk32_mipi_dsi.c @@ -692,7 +692,11 @@ static int rk312x_phy_init(struct dsi *dsi, int n) */ if (dsi->phy.ddr_clk >= 800*MHz) { - rk32_dsi_set_bits(dsi, 0x30, DSI_DPHY_BITS(0x05<<2, 32, 0)); + if (dsi->ops.id == DWC_DSI_VERSION_RK3368) { + rk32_dsi_set_bits(dsi, 0x10, DSI_DPHY_BITS(0x05<<2, 32, 0)); + } else { + rk32_dsi_set_bits(dsi, 0x30, DSI_DPHY_BITS(0x05<<2, 32, 0)); + } } else { rk32_dsi_set_bits(dsi, 1, reg_da_ppfc); } @@ -722,8 +726,11 @@ static int rk312x_phy_init(struct dsi *dsi, int n) rk32_dsi_set_bits(dsi, 0x0063, reg10_phy); */ - - rk32_dsi_set_bits(dsi, 0x06, reg5_phy); + if (dsi->ops.id == DWC_DSI_VERSION_RK3368) { + rk32_dsi_set_bits(dsi, 0x1, reg5_phy); + } else { + rk32_dsi_set_bits(dsi, 0x6, reg5_phy); + } rk32_dsi_set_bits(dsi, 0x6, reg10_4_6_phy); rk32_dsi_set_bits(dsi, 0x9, regb_phy); return 0; -- 2.34.1