From 060d182bfa9a34e974eb4a81989cf5d4b1d986d1 Mon Sep 17 00:00:00 2001 From: William Wu Date: Wed, 17 May 2017 16:34:38 +0800 Subject: [PATCH] phy: rockchip-inno-usb2: add cfgs for phy1 port1 of rk322x SoC This patch adds port configuration for usb2 phy1 port1 of rk322x SoC. For the current rockchip inno usb2 phy driver framework, it can only support usb2 phy which comprises with one otg-port and one host-port. However, rk322x SoC usb2 phy1 comprises with two host-ports, so we use otg id index for phy1 port1 configuration, and make phy1 port1 work the same as otg-port host mode. Change-Id: Iaa10c2438c6b7b052c7f3830252ba4ebd91ff23f Signed-off-by: William Wu --- drivers/phy/phy-rockchip-inno-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c index ad9561b7ea33..e005fa52d77a 100644 --- a/drivers/phy/phy-rockchip-inno-usb2.c +++ b/drivers/phy/phy-rockchip-inno-usb2.c @@ -445,6 +445,7 @@ static int rockchip_usb2phy_init(struct phy *phy) if (rport->port_id == USB2PHY_PORT_OTG) { if (rport->mode != USB_DR_MODE_HOST && + rport->mode != USB_DR_MODE_UNKNOWN && !rport->vbus_always_on) { /* clear bvalid status and enable bvalid detect irq */ ret = property_enable(rphy, @@ -568,6 +569,7 @@ static int rockchip_usb2phy_exit(struct phy *phy) if (rport->port_id == USB2PHY_PORT_OTG && rport->mode != USB_DR_MODE_HOST && + rport->mode != USB_DR_MODE_UNKNOWN && !rport->vbus_always_on) cancel_delayed_work_sync(&rport->chg_work); else if (rport->port_id == USB2PHY_PORT_HOST) @@ -1180,7 +1182,8 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, } rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); - if (rport->mode == USB_DR_MODE_HOST) { + if (rport->mode == USB_DR_MODE_HOST || + rport->mode == USB_DR_MODE_UNKNOWN) { if (rphy->edev_self) { extcon_set_state(rphy->edev, EXTCON_USB, false); extcon_set_state(rphy->edev, EXTCON_USB_HOST, true); @@ -1593,6 +1596,12 @@ static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { .num_ports = 2, .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, + .ls_det_en = { 0x0684, 1, 1, 0, 1 }, + .ls_det_st = { 0x0694, 1, 1, 0, 1 }, + .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } + }, [USB2PHY_PORT_HOST] = { .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, .ls_det_en = { 0x0684, 0, 0, 0, 1 }, -- 2.34.1