From 06c51569237a6996df61474429ce914e6efdb2e0 Mon Sep 17 00:00:00 2001 From: xbw Date: Fri, 21 Mar 2014 01:17:21 +0800 Subject: [PATCH] SDMMC: open the 8bit bus width and IDMA --- arch/arm/configs/rockchip_defconfig | 2 ++ drivers/mmc/host/dw_mmc-rockchip.c | 2 +- drivers/mmc/host/rk_sdmmc.c | 10 ++++------ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/configs/rockchip_defconfig b/arch/arm/configs/rockchip_defconfig index 486e456a8341..b6ae83c2faf8 100755 --- a/arch/arm/configs/rockchip_defconfig +++ b/arch/arm/configs/rockchip_defconfig @@ -453,6 +453,8 @@ CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_BLOCK_MINORS=32 # CONFIG_MMC_BLOCK_BOUNCE is not set CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 4f9a3d058801..7b4c13331651 100755 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -160,7 +160,7 @@ static int dw_mci_rockchip_parse_dt(struct dw_mci *host) /* Common capabilities of RK32XX SoC */ static unsigned long rockchip_dwmmc_caps[4] = { /*MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR | //Temporarily comment out!!!!!!, deleted by xbw, at 2014-03-12*/ - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50, + MMC_CAP_8_BIT_DATA|MMC_CAP_4_BIT_DATA|MMC_CAP_CMD23|MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50|MMC_CAP_UHS_SDR104|MMC_CAP_ERASE, MMC_CAP_CMD23, MMC_CAP_CMD23, MMC_CAP_CMD23, diff --git a/drivers/mmc/host/rk_sdmmc.c b/drivers/mmc/host/rk_sdmmc.c index 803a0eafa053..de7b375b6b50 100755 --- a/drivers/mmc/host/rk_sdmmc.c +++ b/drivers/mmc/host/rk_sdmmc.c @@ -420,8 +420,8 @@ static void dw_mci_idmac_complete_dma(struct dw_mci *host) struct mmc_data *data = host->data; dev_vdbg(host->dev, "DMA complete\n"); - MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \ - host->cmd->opcode,host->cmd->arg,data->blocks,data->blksz,mmc_hostname(host->mmc)); + // MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \ + // host->mrq->cmd->opcode,host->mrq->cmd->arg,data->blocks,data->blksz,mmc_hostname(host->mmc)); host->dma_ops->cleanup(host); @@ -1014,12 +1014,10 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->bus_width) { case MMC_BUS_WIDTH_4: slot->ctype = SDMMC_CTYPE_4BIT; - break; -#if 0//test, use sd to emmc + break; case MMC_BUS_WIDTH_8: slot->ctype = SDMMC_CTYPE_8BIT; - break; -#endif + break; default: /* set default 1 bit mode */ slot->ctype = SDMMC_CTYPE_1BIT; -- 2.34.1