From 08998398e1a940c8fa2d83fc7aadd44dd85b3870 Mon Sep 17 00:00:00 2001 From: chenxing Date: Thu, 21 Mar 2013 17:31:30 +0800 Subject: [PATCH] rk3188: support hdmi 576p(dclk_lcdc freediv when need 27 MHz) --- arch/arm/mach-rk3188/clock_data.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c index eeac5f89e0ff..72da5601d357 100755 --- a/arch/arm/mach-rk3188/clock_data.c +++ b/arch/arm/mach-rk3188/clock_data.c @@ -1549,9 +1549,14 @@ static int clksel_set_rate_hdmi(struct clk *clk, unsigned long rate) static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate) { + if (rate == 27 * MHZ) + return clkset_rate_freediv_autosel_parents(clk, rate); + else + return clkset_rate_evendiv_autosel_parents(clk, rate); + +#if 0 int ret = 0; struct clk *parent; - if (rate == 27 * MHZ && (rk30_clock_flags & CLK_FLG_EXT_27MHZ)) { parent = clk->parents[1]; //CLKDATA_DBG(" %s from=%s\n",clk->name,parent->name); @@ -1576,13 +1581,14 @@ static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate) } } return ret; +#endif } static struct clk *dclk_lcdc0_parents[2] = {&codec_pll_clk, &general_pll_clk}; static struct clk dclk_lcdc0 = { .name = "dclk_lcdc0", .mode = gate_mode, - .set_rate = clkset_rate_evendiv_autosel_parents, + .set_rate = dclk_lcdc_set_rate, .recalc = clksel_recalc_div, .gate_idx = CLK_GATE_DCLK_LCDC0_SRC, .clksel_con = CRU_CLKSELS_CON(27), @@ -1595,7 +1601,7 @@ static struct clk *dclk_lcdc1_parents[2] = {&codec_pll_clk, &general_pll_clk}; static struct clk dclk_lcdc1 = { .name = "dclk_lcdc1", .mode = gate_mode, - .set_rate = clkset_rate_evendiv_autosel_parents, + .set_rate = dclk_lcdc_set_rate, .recalc = clksel_recalc_div, .gate_idx = CLK_GATE_DCLK_LCDC1_SRC, .clksel_con = CRU_CLKSELS_CON(28), -- 2.34.1