From 08b84034cce0da0bc6ce7390d71cbd56e664857c Mon Sep 17 00:00:00 2001 From: "Huang, Tao" Date: Fri, 21 Nov 2014 14:00:14 +0800 Subject: [PATCH] ARM: rockchip: rk3126b: add initial support --- arch/arm/kernel/pie.lds.S | 1 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/cpu.c | 2 +- arch/arm/mach-rockchip/ddr_rk3126.c | 45 +++++---------- arch/arm/mach-rockchip/dvfs.c | 2 +- arch/arm/mach-rockchip/pm-rk312x.c | 2 +- arch/arm/mach-rockchip/rk3126b.c | 82 +++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3126b.h | 6 ++ arch/arm/mach-rockchip/rk312x.c | 88 ++++++++++++++++------------- drivers/mmc/host/rk_sdmmc.c | 10 ++-- include/linux/rockchip/cpu.h | 2 + pie/Makefile | 1 + 12 files changed, 163 insertions(+), 79 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3126b.c create mode 100644 arch/arm/mach-rockchip/rk3126b.h diff --git a/arch/arm/kernel/pie.lds.S b/arch/arm/kernel/pie.lds.S index 0652f8e8f737..76bfbf68c2f3 100755 --- a/arch/arm/kernel/pie.lds.S +++ b/arch/arm/kernel/pie.lds.S @@ -38,6 +38,7 @@ SECTIONS PIE_OVERLAY_SECTION(rk3188) PIE_OVERLAY_SECTION(rk3036) PIE_OVERLAY_SECTION(rk312x) + PIE_OVERLAY_SECTION(rk3126b) } PIE_OVERLAY_END diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 60abbe9eea31..1c5d87f3f4d8 100755 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -2,6 +2,7 @@ obj-y += common.o obj-y += cpu.o obj-y += rk3036.o obj-y += rk312x.o +obj-y += rk3126b.o obj-y += rk3188.o obj-y += rk3288.o obj-y += ddr_freq.o diff --git a/arch/arm/mach-rockchip/cpu.c b/arch/arm/mach-rockchip/cpu.c index a8b4c226a52d..69bed0f0c6f0 100644 --- a/arch/arm/mach-rockchip/cpu.c +++ b/arch/arm/mach-rockchip/cpu.c @@ -71,7 +71,7 @@ static ssize_t soc_show(struct device *dev, struct device_attribute *attr, char soc = "rk3068"; else if (soc_is_rk3000()) soc = "rk3000"; - else if (soc_is_rk3126()) + else if (soc_is_rk3126() || soc_is_rk3126b()) soc = "rk3126"; else if (soc_is_rk3128()) soc = "rk3128"; diff --git a/arch/arm/mach-rockchip/ddr_rk3126.c b/arch/arm/mach-rockchip/ddr_rk3126.c index 2c7df7fce169..7e77d7cae8e8 100755 --- a/arch/arm/mach-rockchip/ddr_rk3126.c +++ b/arch/arm/mach-rockchip/ddr_rk3126.c @@ -734,7 +734,7 @@ static uint32 *p_ddr_freq; uint32 DEFINE_PIE_DATA(ddr_sr_idle); uint32 DEFINE_PIE_DATA(ddr_dll_status); /* ¼Ç¼ddr dllµÄ״̬£¬ÔÚselfrefresh exitʱѡÔñÊÇ·ñ½øÐÐdll reset*/ -uint32_t ddr3_cl_cwl[22][4] = { +static const uint32_t ddr3_cl_cwl[22][4] = { /* 0~330 330~400 400~533 speed * tCK >3 2.5~3 1.875~2.5 1.875~1.5 * cl<<16, cwl cl<<16, cwl cl<<16, cwl */ @@ -768,7 +768,7 @@ uint32_t ddr3_cl_cwl[22][4] = { {((6 << 16) | 5), ((6 << 16) | 5), ((8 << 16) | 6), ((10 << 16) | 7)} /*DDR3_DEFAULT*/ }; -uint32_t ddr3_tRC_tFAW[22] = { +static const uint32_t ddr3_tRC_tFAW[22] = { /** tRC tFAW */ ((50 << 16) | 50), /*DDR3_800D*/ ((53 << 16) | 50), /*DDR3_800E*/ @@ -989,7 +989,7 @@ __sramdata uint32 copy_data[8] = { }; EXPORT_PIE_SYMBOL(copy_data[8]); -uint32 *p_copy_data; +static uint32 *p_copy_data; /*---------------------------------------------------------------------- Name : uint32_t __sramlocalfunc ddr_data_training(void) @@ -2069,11 +2069,9 @@ static void __sramfunc ddr_selfrefresh_enter(uint32 nMHz) pCRU_Reg->CRU_CLKGATE_CON[0] = ((0x1 << 2) << 16) | (1 << 2); /*disable DDR PHY clock*/ ddr_delayus(1); } - -/*EXPORT_SYMBOL(ddr_selfrefresh_enter);*/ #endif -uint32 dtt_buffer[8]; +static uint32 dtt_buffer[8]; /*---------------------------------------------------------------------- *Name : void ddr_dtt_check(void) @@ -2082,7 +2080,7 @@ uint32 dtt_buffer[8]; *Return : void *Notes : *----------------------------------------------------------------------*/ -void ddr_dtt_check(void) +static void ddr_dtt_check(void) { uint32 i; for (i = 0; i < 8; i++) { @@ -2131,7 +2129,7 @@ static void __sramfunc ddr_selfrefresh_exit(void) *Return : void *Notes : *----------------------------------------------------------------------*/ -void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew) +static void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew) { uint32 value_100n, value_1u; @@ -2160,7 +2158,7 @@ void __sramlocalfunc ddr_change_freq_in(uint32 freq_slew) *Return : void *Notes : *----------------------------------------------------------------------*/ -void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew) +static void __sramlocalfunc ddr_change_freq_out(uint32 freq_slew) { if (freq_slew == 1) { pDDR_Reg->TOGCNT100N = DATA(ddr_reg).pctl_timing.togcnt100n; @@ -2462,8 +2460,6 @@ static int _ddr_change_freq(uint32 nMHz) return ret; } -EXPORT_SYMBOL(_ddr_change_freq); - /*---------------------------------------------------------------------- *Name : void ddr_set_auto_self_refresh(bool en) *Desc : ÉèÖýøÈë selfrefesh µÄÖÜÆÚÊý @@ -2471,14 +2467,12 @@ EXPORT_SYMBOL(_ddr_change_freq); *Return : ƵÂÊÖµ *Notes : ÖÜÆÚÊýΪ1*32 cycle *----------------------------------------------------------------------*/ -void _ddr_set_auto_self_refresh(bool en) +static void _ddr_set_auto_self_refresh(bool en) { /*set auto self-refresh idle */ *kern_to_pie(rockchip_pie_chunk, &DATA(ddr_sr_idle)) = en ? SR_IDLE : 0; } -EXPORT_SYMBOL(_ddr_set_auto_self_refresh); - /*---------------------------------------------------------------------- *Name : void __sramfunc ddr_suspend(void) *Desc : ½øÈëddr suspend @@ -2486,7 +2480,6 @@ EXPORT_SYMBOL(_ddr_set_auto_self_refresh); *Return : void *Notes : *----------------------------------------------------------------------*/ -#if 1 void PIE_FUNC(ddr_suspend)(void) { ddr_selfrefresh_enter(0); @@ -2501,7 +2494,8 @@ void PIE_FUNC(ddr_suspend)(void) EXPORT_PIE_SYMBOL(FUNC(ddr_suspend)); -void ddr_suspend(void) +#if 0 +static void ddr_suspend(void) { uint32 i; volatile uint32 n; @@ -2525,11 +2519,8 @@ void ddr_suspend(void) fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_suspend)) (); } - -EXPORT_SYMBOL(ddr_suspend); #endif -#if 1 /*---------------------------------------------------------------------- *Name : void __sramfunc ddr_resume(void) *Desc : ddr resume @@ -2558,12 +2549,11 @@ void PIE_FUNC(ddr_resume)(void) EXPORT_PIE_SYMBOL(FUNC(ddr_resume)); -void ddr_resume(void) +#if 0 +static void ddr_resume(void) { fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_resume)) (); } - -EXPORT_SYMBOL(ddr_resume); #endif /*---------------------------------------------------------------------- @@ -2573,7 +2563,7 @@ EXPORT_SYMBOL(ddr_resume); *Return : ¿ÅÁ£ÈÝÁ¿ *Notes : *----------------------------------------------------------------------*/ -uint32 ddr_get_cap(void) +static uint32 ddr_get_cap(void) { uint32 cs, bank, row, col, row1, bw; @@ -2591,8 +2581,6 @@ uint32 ddr_get_cap(void) } } -EXPORT_SYMBOL(ddr_get_cap); - static long _ddr_round_rate(uint32 nMHz) { return p_ddr_set_pll(nMHz, 0); @@ -2615,7 +2603,7 @@ static void ddr_dfi_monitor_stop(void) pGRF_Reg->GRF_SOC_CON[0] = DDR_MONITOR_DISB; } -void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_info *ddr_bw_ch1) +static void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_info *ddr_bw_ch1) { uint32 ddr_bw_val[ddrbw_id_end], ddr_freq; u64 temp64; @@ -2643,7 +2631,6 @@ void _ddr_bandwidth_get(struct ddr_bw_info *ddr_bw_ch0, struct ddr_bw_info *ddr_ end: ddr_dfi_monitor_strat(); } -EXPORT_SYMBOL(_ddr_bandwidth_get); /*---------------------------------------------------------------------- *Name : int ddr_init(uint32_t dram_speed_bin, uint32_t freq) @@ -2653,7 +2640,7 @@ EXPORT_SYMBOL(_ddr_bandwidth_get); *Return : 0 ³É¹¦ *Notes : *----------------------------------------------------------------------*/ -int ddr_init(uint32_t dram_speed_bin, uint32 freq) +static int ddr_init(uint32_t dram_speed_bin, uint32 freq) { uint32_t value = 0; uint32_t cs, die = 1; @@ -2708,5 +2695,3 @@ int ddr_init(uint32_t dram_speed_bin, uint32 freq) return 0; } - -EXPORT_SYMBOL(ddr_init); diff --git a/arch/arm/mach-rockchip/dvfs.c b/arch/arm/mach-rockchip/dvfs.c index 0944f56230a6..85a7699bd2ed 100644 --- a/arch/arm/mach-rockchip/dvfs.c +++ b/arch/arm/mach-rockchip/dvfs.c @@ -1021,7 +1021,7 @@ static void dvfs_virt_temp_limit_work_func(void) static bool in_perf; int i; - if (!soc_is_rk3126() && !soc_is_rk3128()) + if (!cpu_is_rk312x()) return; if (rockchip_get_system_status() & SYS_STATUS_PERFORMANCE) { diff --git a/arch/arm/mach-rockchip/pm-rk312x.c b/arch/arm/mach-rockchip/pm-rk312x.c index 1a26cc5a59b4..0a511a8fb3cf 100644 --- a/arch/arm/mach-rockchip/pm-rk312x.c +++ b/arch/arm/mach-rockchip/pm-rk312x.c @@ -602,7 +602,7 @@ static void rkpm_save_setting(u32 ctrbits) #define UART_LCR 3 /* Out: Line Control Register */ #define UART_MCR 4 -void slp312x_uartdbg_resume(void) +static void slp312x_uartdbg_resume(void) { void __iomem *b_addr = RK_DEBUG_UART_VIRT; u32 pclk_id = RK312X_CLKGATE_PCLK_UART2; diff --git a/arch/arm/mach-rockchip/rk3126b.c b/arch/arm/mach-rockchip/rk3126b.c new file mode 100644 index 000000000000..160c520ef2a1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3126b.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3126b.h" +#define CPU 3126b +#include "sram.h" +#include "pm.h" +#include "pm-rk312x.c" + +char PIE_DATA(sram_stack)[1024]; +EXPORT_PIE_SYMBOL(DATA(sram_stack)); + +static int __init rk3126b_pie_init(void) +{ + int err; + + if (!soc_is_rk3126b()) + return 0; + + err = rockchip_pie_init(); + if (err) + return err; + + rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3126b); + if (IS_ERR(rockchip_pie_chunk)) { + err = PTR_ERR(rockchip_pie_chunk); + pr_err("%s: failed to load section %d\n", __func__, err); + rockchip_pie_chunk = NULL; + return err; + } + + rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]); + rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack))); + + return 0; +} +arch_initcall(rk3126b_pie_init); + +#ifdef CONFIG_PM +void __init rk3126b_init_suspend(void) +{ + pr_info("%s\n", __func__); + rkpm_pie_init(); + rk312x_suspend_init(); +} +#endif + +#include "ddr_rk3126.c" +static int __init rk3126b_ddr_init(void) +{ + if (!soc_is_rk3126b()) + return 0; + + ddr_change_freq = _ddr_change_freq; + ddr_round_rate = _ddr_round_rate; + ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh; + ddr_bandwidth_get = _ddr_bandwidth_get; + ddr_init(DDR3_DEFAULT, 300); + + return 0; +} +arch_initcall_sync(rk3126b_ddr_init); diff --git a/arch/arm/mach-rockchip/rk3126b.h b/arch/arm/mach-rockchip/rk3126b.h new file mode 100644 index 000000000000..188561cd5773 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3126b.h @@ -0,0 +1,6 @@ +#ifndef __MACH_ROCKCHIP_RK3126B_H +#define __MACH_ROCKCHIP_RK3126B_H + +void __init rk3126b_init_suspend(void); + +#endif diff --git a/arch/arm/mach-rockchip/rk312x.c b/arch/arm/mach-rockchip/rk312x.c index 7c8f69acbc65..5bdb9dfb2483 100755 --- a/arch/arm/mach-rockchip/rk312x.c +++ b/arch/arm/mach-rockchip/rk312x.c @@ -1,6 +1,4 @@ /* - * Device Tree support for Rockchip RK3288 - * * Copyright (C) 2014 ROCKCHIP, Inc. * * This program is free software; you can redistribute it and/or modify @@ -36,6 +34,7 @@ #include #include "cpu_axi.h" #include "loader.h" +#include "rk3126b.h" #define CPU 312x #include "sram.h" #include "pm.h" @@ -152,6 +151,9 @@ static void __init rk3126_dt_map_io(void) rockchip_soc_id = ROCKCHIP_SOC_RK3126; rk312x_dt_map_io(); + + if (readl_relaxed(RK_GRF_VIRT + RK312X_GRF_CHIP_TAG) == 0x3136) + rockchip_soc_id = ROCKCHIP_SOC_RK3126B; } static void __init rk3128_dt_map_io(void) @@ -351,13 +353,52 @@ static void __init rk312x_reserve(void) /* reserve memory for ION */ rockchip_ion_reserve(); } + #ifdef CONFIG_PM -static void __init rk321x_init_suspend(void); +static u32 rk_pmu_pwrdn_st; + +static void rk_pm_soc_pd_suspend(void) +{ + rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST); + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU]))) + rk312x_sys_set_power_domain(PD_GPU, false); + + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO]))) + rk312x_sys_set_power_domain(PD_VIO, false); + + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO]))) + rk312x_sys_set_power_domain(PD_VIDEO, false); +} + +static void rk_pm_soc_pd_resume(void) +{ + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO]))) + rk312x_sys_set_power_domain(PD_VIDEO, true); + + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO]))) + rk312x_sys_set_power_domain(PD_VIO, true); + + if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU]))) + rk312x_sys_set_power_domain(PD_GPU, true); +} + +static void __init rk312x_init_suspend(void) +{ + pr_info("%s\n", __func__); + rkpm_pie_init(); + rk312x_suspend_init(); +} #endif + static void __init rk312x_init_late(void) { #ifdef CONFIG_PM - rk321x_init_suspend(); + rockchip_suspend_init(); + if (soc_is_rk3126b()) + rk3126b_init_suspend(); + else + rk312x_init_suspend(); + rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume); #endif if (rockchip_jtag_enabled) clk_prepare_enable(clk_get_sys(NULL, "clk_jtag")); @@ -413,6 +454,8 @@ static int __init rk312x_pie_init(void) if (!cpu_is_rk312x()) return 0; + if (soc_is_rk3126b()) + return 0; err = rockchip_pie_init(); if (err) @@ -436,7 +479,7 @@ arch_initcall(rk312x_pie_init); #include "ddr_rk3126.c" static int __init rk312x_ddr_init(void) { - if (cpu_is_rk312x()) { + if (soc_is_rk3128() || soc_is_rk3126()) { ddr_change_freq = _ddr_change_freq; ddr_round_rate = _ddr_round_rate; ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh; @@ -446,38 +489,3 @@ static int __init rk312x_ddr_init(void) return 0; } arch_initcall_sync(rk312x_ddr_init); - -#ifdef CONFIG_PM -static u32 rk_pmu_pwrdn_st; -static inline void rk_pm_soc_pd_suspend(void) -{ - rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST); - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU]))) - rk312x_sys_set_power_domain(PD_GPU, false); - - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO]))) - rk312x_sys_set_power_domain(PD_VIO, false); - - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO]))) - rk312x_sys_set_power_domain(PD_VIDEO, false); -} -static inline void rk_pm_soc_pd_resume(void) -{ - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO]))) - rk312x_sys_set_power_domain(PD_VIDEO, true); - - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO]))) - rk312x_sys_set_power_domain(PD_VIO, true); - - if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU]))) - rk312x_sys_set_power_domain(PD_GPU, true); -} -static void __init rk321x_init_suspend(void) -{ - pr_info("%s\n", __func__); - rockchip_suspend_init(); - rkpm_pie_init(); - rk312x_suspend_init(); - rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume); -} -#endif diff --git a/drivers/mmc/host/rk_sdmmc.c b/drivers/mmc/host/rk_sdmmc.c index 62c18d898fe5..a67adfdef224 100755 --- a/drivers/mmc/host/rk_sdmmc.c +++ b/drivers/mmc/host/rk_sdmmc.c @@ -1540,8 +1540,7 @@ static int dw_mci_get_cd(struct mmc_host *mmc) int gpio_cd = mmc_gpio_get_cd(mmc); int gpio_val; - if (cpu_is_rk312x() && - soc_is_rk3126() && + if ((soc_is_rk3126() || soc_is_rk3126b()) && (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) { gpio_cd = slot->cd_gpio; if (gpio_is_valid(gpio_cd)) { @@ -3434,8 +3433,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) } /* We assume only low-level chip use gpio_cd */ - if (cpu_is_rk312x() && - soc_is_rk3126() && + if ((soc_is_rk3126() || soc_is_rk3126b()) && (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) { slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0); if (gpio_is_valid(slot->cd_gpio)) { @@ -4189,7 +4187,7 @@ int dw_mci_suspend(struct dw_mci *host) mci_writel(host, CTRL, 0x00); /* Soc rk3126 already in gpio_cd mode */ - if (!(cpu_is_rk312x() && soc_is_rk3126())) { + if (!soc_is_rk3126() && !soc_is_rk3126b()) { dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc); enable_irq_wake(host->mmc->slot.cd_irq); } @@ -4219,7 +4217,7 @@ int dw_mci_resume(struct dw_mci *host) /*only for sdmmc controller*/ if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) { /* Soc rk3126 already in gpio_cd mode */ - if (!(cpu_is_rk312x() && soc_is_rk3126())) { + if (!soc_is_rk3126() && !soc_is_rk3126b()) { disable_irq_wake(host->mmc->slot.cd_irq); mmc_gpio_free_cd(host->mmc); } diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index 1c7966add6ad..3b3faa71d93e 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -58,6 +58,7 @@ ROCKCHIP_CPU(3288, 3288) #define ROCKCHIP_SOC_RK3028A (ROCKCHIP_CPU_RK3026 | 0x03) #define ROCKCHIP_SOC_RK3026 (ROCKCHIP_CPU_RK3026 | 0x04) #define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK312X | 0x00) +#define ROCKCHIP_SOC_RK3126B (ROCKCHIP_CPU_RK312X | 0x10) #define ROCKCHIP_SOC_RK3128 (ROCKCHIP_CPU_RK312X | 0x01) #define ROCKCHIP_SOC_RK3036 (ROCKCHIP_CPU_RK3036 | 0x00) #define ROCKCHIP_SOC_RK3000 (ROCKCHIP_CPU_RK30XX | 0x00) @@ -83,6 +84,7 @@ ROCKCHIP_SOC(2928l, 2928L) ROCKCHIP_SOC(3028a, 3028A) ROCKCHIP_SOC(3026, 3026) ROCKCHIP_SOC(3126, 3126) +ROCKCHIP_SOC(3126b, 3126B) ROCKCHIP_SOC(3128, 3128) ROCKCHIP_SOC(3036, 3036) ROCKCHIP_SOC(3000, 3000) diff --git a/pie/Makefile b/pie/Makefile index 34aec9a55f8d..a3223d4becff 100644 --- a/pie/Makefile +++ b/pie/Makefile @@ -65,6 +65,7 @@ OBJCOPYFLAGS_pie_stage3.o += -j ".pie.*" OBJCOPYFLAGS_pie_stage3.o += -j ".pie.text" OBJCOPYFLAGS_pie_stage3.o += -j ".pie.rk3036.text" -j ".pie.rk3036.data" OBJCOPYFLAGS_pie_stage3.o += -j ".pie.rk312x.text" -j ".pie.rk312x.data" +OBJCOPYFLAGS_pie_stage3.o += -j ".pie.rk3126b.text" -j ".pie.rk3126b.data" OBJCOPYFLAGS_pie_stage3.o += -j ".pie.rk3188.text" -j ".pie.rk3188.data" OBJCOPYFLAGS_pie_stage3.o += -j ".pie.rk3288.text" -j ".pie.rk3288.data" -- 2.34.1