From 09af8dc558974031a281b1491dad25df8a9d672f Mon Sep 17 00:00:00 2001 From: root Date: Fri, 10 Jun 2011 17:38:57 +0800 Subject: [PATCH] edit system suspend vol control code --- arch/arm/mach-rk29/Kconfig | 11 +- arch/arm/mach-rk29/Makefile | 3 +- arch/arm/mach-rk29/include/mach/pm-vol.h | 21 ++ arch/arm/mach-rk29/pm.c | 79 +--- arch/arm/mach-rk29/pwm_sram.c | 84 +++++ arch/arm/mach-rk29/spi_sram.c | 457 ++++++++++++++++++----- 6 files changed, 480 insertions(+), 175 deletions(-) create mode 100644 arch/arm/mach-rk29/include/mach/pm-vol.h create mode 100644 arch/arm/mach-rk29/pwm_sram.c diff --git a/arch/arm/mach-rk29/Kconfig b/arch/arm/mach-rk29/Kconfig index 91433adc823a..248bdb3e0a0c 100644 --- a/arch/arm/mach-rk29/Kconfig +++ b/arch/arm/mach-rk29/Kconfig @@ -179,8 +179,15 @@ config RK29_LAST_LOG default y help It is only intended for debugging. -config RK29_SRAM_SPI - tristate "Support spi driver codec run in sram" +menu "The control interface support for RK29 suspend " +config RK29_SPI_INSRAM + tristate "Support spi control interface" + depends on REGULATOR_WM831X default n +config RK29_PWM_INSRAM + tristate "Support pwm control interface" + depends on RK29_PWM_REGULATOR + default y +endmenu endif diff --git a/arch/arm/mach-rk29/Makefile b/arch/arm/mach-rk29/Makefile index fc77b8e9baf5..39a6a7e66e20 100644 --- a/arch/arm/mach-rk29/Makefile +++ b/arch/arm/mach-rk29/Makefile @@ -9,7 +9,8 @@ obj-$(CONFIG_USB_GADGET) += usb_detect.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_RK29_VPU) += vpu.o vpu_mem.o -obj-$(CONFIG_RK29_SRAM_SPI) += spi_sram.o +obj-$(CONFIG_RK29_SPI_INSRAM) += spi_sram.o +obj-$(CONFIG_RK29_PWM_INSRAM) += pwm_sram.o obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o obj-$(CONFIG_MACH_RK29SDK_DDR3) += board-rk29-ddr3sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o obj-$(CONFIG_MACH_RK29WINACCORD) += board-rk29-winaccord.o board-rk29sdk-key.o diff --git a/arch/arm/mach-rk29/include/mach/pm-vol.h b/arch/arm/mach-rk29/include/mach/pm-vol.h new file mode 100644 index 000000000000..b265f656c6af --- /dev/null +++ b/arch/arm/mach-rk29/include/mach/pm-vol.h @@ -0,0 +1,21 @@ +#ifndef PM_VOL_H +#define PM_VOL_H + + +#if defined(CONFIG_RK29_SPI_INSRAM)||defined(CONFIG_RK29_PWM_INSRAM) + +void interface_ctr_reg_pread(void); +unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol); +void __sramfunc rk29_suspend_voltage_resume(unsigned int vol); + +#else + +#define interface_ctr_reg_pread() +static unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol) +{ +} +#define rk29_suspend_voltage_resume(a) + +#endif + +#endif diff --git a/arch/arm/mach-rk29/pm.c b/arch/arm/mach-rk29/pm.c index 9aab0ef6cd38..db55f2f27a9f 100644 --- a/arch/arm/mach-rk29/pm.c +++ b/arch/arm/mach-rk29/pm.c @@ -9,9 +9,6 @@ #include #include #include -#ifdef CONFIG_RK29_PWM_REGULATOR -#include -#endif #include #include #include @@ -26,18 +23,8 @@ #include #include #include - #include - -#if defined(CONFIG_RK29_SRAM_SPI) -void sram_spi_pread(void); -void __sramfunc rk29_spi_ctr_vol_sleep(void); -void __sramfunc rk29_spi_ctr_vol_resume(void); -#else -#define sram_spi_pread() -#define rk29_spi_ctr_vol_sleep() -#define rk29_spi_ctr_vol_resume() -#endif +#include #define grf_readl(offset) readl(RK29_GRF_BASE + offset) #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0) @@ -151,42 +138,6 @@ static void inline printascii(const char *s) {} static void inline printhex(unsigned int hex) {} #endif /* DEBUG */ -#ifdef CONFIG_RK29_PWM_REGULATOR -#define pwm_write_reg(addr, val) __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10)) -#define pwm_read_reg(addr) __raw_readl(addr + (RK29_PWM_BASE + 2*0x10)) - -static u32 __sramdata pwm_lrc, pwm_hrc; -static void __sramfunc rk29_set_core_voltage(int uV) -{ - u32 gate1; - - gate1 = cru_readl(CRU_CLKGATE1_CON); - cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON); - - /* iomux pwm2 */ - writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58); - - if (uV) { - pwm_lrc = pwm_read_reg(PWM_REG_LRC); - pwm_hrc = pwm_read_reg(PWM_REG_HRC); - } - - pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET); - if (uV == 1000000) { - pwm_write_reg(PWM_REG_LRC, 12); - pwm_write_reg(PWM_REG_HRC, 10); - } else { - pwm_write_reg(PWM_REG_LRC, pwm_lrc); - pwm_write_reg(PWM_REG_HRC, pwm_hrc); - } - pwm_write_reg(PWM_REG_CNTR, 0); - pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN); - - LOOP(5 * 1000 * LOOPS_PER_USEC); /* delay 5ms */ - - cru_writel(gate1, CRU_CLKGATE1_CON); -} -#endif /* CONFIG_RK29_PWM_REGULATOR */ /*volatile __sramdata */int ddr_debug; module_param(ddr_debug, int, 0644); #if 1 @@ -277,6 +228,7 @@ void __sramfunc ddr_testmode(void) static void __sramfunc rk29_sram_suspend(void) { u32 clksel0; + u32 vol; if ((ddr_debug == 1) || (ddr_debug == 2)) ddr_testmode(); @@ -285,13 +237,7 @@ static void __sramfunc rk29_sram_suspend(void) ddr_suspend(); printch('6'); -#ifdef CONFIG_RK29_PWM_REGULATOR - rk29_set_core_voltage(1000000); -#endif -#if defined(CONFIG_RK29_SRAM_SPI) - rk29_spi_ctr_vol_sleep(); -#endif - + vol=rk29_suspend_voltage_set(1000000); printch('7'); clksel0 = cru_readl(CRU_CLKSEL0_CON); /* set arm clk 24MHz/32 = 750KHz */ @@ -306,12 +252,8 @@ static void __sramfunc rk29_sram_suspend(void) cru_writel(clksel0, CRU_CLKSEL0_CON); printch('7'); -#ifdef CONFIG_RK29_PWM_REGULATOR - rk29_set_core_voltage(0); -#endif -#if defined(CONFIG_RK29_SRAM_SPI) - rk29_spi_ctr_vol_resume(); -#endif + rk29_suspend_voltage_resume(vol); + printch('6'); @@ -409,13 +351,8 @@ static int rk29_pm_enter(suspend_state_t state) #endif printch('0'); + interface_ctr_reg_pread(); -#ifdef CONFIG_RK29_PWM_REGULATOR - /* touch TLB */ - flush_tlb_all(); - readl(RK29_PWM_BASE); - readl(RK29_GRF_BASE); -#endif /* disable clock */ clkgate[0] = cru_readl(CRU_CLKGATE0_CON); @@ -486,9 +423,7 @@ static int rk29_pm_enter(suspend_state_t state) delay_500ns(); /* set aclk_periph = hclk_periph = pclk_periph = 24MHz */ cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON); -#if defined(CONFIG_RK29_SRAM_SPI) - sram_spi_pread(); -#endif + printch('4'); rk29_suspend(); diff --git a/arch/arm/mach-rk29/pwm_sram.c b/arch/arm/mach-rk29/pwm_sram.c new file mode 100644 index 000000000000..ce837739f7fb --- /dev/null +++ b/arch/arm/mach-rk29/pwm_sram.c @@ -0,0 +1,84 @@ + +#include +#include +#include +#include +#include +#include +#include + +#define pwm_write_reg(addr, val) __raw_writel(val, addr + (RK29_PWM_BASE + 2*0x10)) +#define pwm_read_reg(addr) __raw_readl(addr + (RK29_PWM_BASE + 2*0x10)) +#define cru_readl(offset) readl(RK29_CRU_BASE + offset) +#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); dsb(); } while (0) + +void interface_ctr_reg_pread(void) +{ + flush_tlb_all(); + readl(RK29_PWM_BASE); + readl(RK29_GRF_BASE); +} +static unsigned int __sramdata pwm_lrc,pwm_hrc; + +static void __sramfunc rk29_pwm_set_core_voltage(unsigned int uV) +{ + u32 gate1; + + gate1 = cru_readl(CRU_CLKGATE1_CON); + cru_writel(gate1 & ~((1 << CLK_GATE_PCLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_PEIRPH % 32) | (1 << CLK_GATE_ACLK_CPU_PERI % 32)), CRU_CLKGATE1_CON); + + /* iomux pwm2 */ + writel((readl(RK29_GRF_BASE + 0x58) & ~(0x3<<6)) | (0x2<<6), RK29_GRF_BASE + 0x58); + + if (uV) { + pwm_lrc = pwm_read_reg(PWM_REG_LRC); + pwm_hrc = pwm_read_reg(PWM_REG_HRC); + } + + pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_RESET); + if (uV == 1000000) { + pwm_write_reg(PWM_REG_LRC, 12); + pwm_write_reg(PWM_REG_HRC, 10); + } else { + pwm_write_reg(PWM_REG_LRC, pwm_lrc); + pwm_write_reg(PWM_REG_HRC, pwm_hrc); + } + pwm_write_reg(PWM_REG_CNTR, 0); + pwm_write_reg(PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN); + + LOOP(5 * 1000 * LOOPS_PER_USEC); /* delay 5ms */ + + cru_writel(gate1, CRU_CLKGATE1_CON); +} + +unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol) +{ + + rk29_pwm_set_core_voltage(1000000); + return 0; + +} +void __sramfunc rk29_suspend_voltage_resume(unsigned int vol) +{ + rk29_pwm_set_core_voltage(0); + return 0; +} + +/* +void interface_ctr_reg_pread(void) +{ +} +unsigned int __sramfunc rk29_suspend_voltage_set(unsigned int vol) +{ +} +void __sramfunc rk29_suspend_voltage_resume(unsigned int vol) +{ +} +*/ + + + + + + + diff --git a/arch/arm/mach-rk29/spi_sram.c b/arch/arm/mach-rk29/spi_sram.c index 2c7eb3358015..7052d3675569 100644 --- a/arch/arm/mach-rk29/spi_sram.c +++ b/arch/arm/mach-rk29/spi_sram.c @@ -1,131 +1,388 @@ -#include +#include +#include +#include +#include -unsigned __sramdata int spibase; -u32 __sramdata spi_base[2]={RK29_SPI0_BASE,RK29_SPI1_BASE}; -u32 __sramdata spi_data[6]={}; -//chcs : &0xf0->ch(spi1spi0), &ox0f->cs(cs1cs0) +#define SPI_KHZ (1000) +#define SPI_MHZ (1000*1000) +#define GPLL_SPEED (24*SPI_MHZ) +#define SPI_SR_SPEED (2*SPI_MHZ) -void __sramfunc delay_test(int delay_time) +#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK) +#define SRAM_SPI_CH 1 +#define SRAM_SPI_CS 1 +#define SRAM_SPI_DATA_BYTE 2 +#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE +#define SPI_SPEED (500*SPI_KHZ) +//#elif defined() +#else +#define SRAM_SPI_CH 1 +#define SRAM_SPI_CS 1 +#define SRAM_SPI_DATA_BYTE 2 +#define SRAM_SPI_ADDRBASE RK29_SPI1_BASE//RK29_SPI0_BASE +#define SPI_SPEED (500*SPI_KHZ) +#endif + +#define SRAM_SPI_SR_DIV (GPLL_SPEED/SPI_SR_SPEED-1) // +#define SRAM_SPI_DIV (SPI_SR_SPEED/SPI_SPEED) + + + + +//#include + +#define SPIM_ENR 0x0008 +#define SPIM_SER 0x000C +#define SPIM_CTRLR0 0x0000 +#define SPIM_BAUDR 0x0010 +#define SPIM_TXFTLR 0x0014 +#define SPIM_RXFLR 0x0020 + +#define SPIM_SR 0x0024 + +#define SPIM_IMR 0x002c +#define SPIM_TXDR 0x400 +#define SPIM_RXDR 0x800 +/* Bit fields in rxflr, */ +#define RXFLR_MASK (0x3f) +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f /* cover 7 bits */ +#define SR_BUSY (1 << 0) +#define SR_TF_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) + + +#define CRU_CLKSEL6_CON 0x2C +#define CRU_CLKGATE2_CON 0x64 +#define CRU_CLKGATE1_CON 0x60 + + + +#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset) +#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE + offset) + +enum +{ +GRF_IOM50=0, +GRF_IOM5c, +CLKGATE1, +CLKGATE2, +CLKSEL6, +SPI_CTRLR0, +SPI_BAUDR, +SPI_SER, +DATE_END, +}; + +/*unsigned int __sramdata spibase; +unsigned int __sramdata sram_spi_cs; +u32 __sramdata spi_base[2]={RK29_SPI0_BASE,RK29_SPI1_BASE};*/ +u32 __sramdata spi_data[DATE_END]={}; +#define sram_spi_dis() spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR) +#define sram_spi_en() spi_writel(spi_readl(SPIM_ENR)|(0x1<<0),SPIM_ENR) +#define sram_spi_cs_dis() spi_writel(spi_readl(SPIM_SER)&~0x3,SPIM_SER) +#define sram_spi_cs_en() spi_writel((spi_readl(SPIM_SER)&~0x3)|(0x1<