From 0a4371a2073d8841768cf3e8cf65601a8d7cc4fc Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Wed, 18 Sep 2013 22:08:59 +0000 Subject: [PATCH] Debug info: Get rid of the VLA indirection hack in FastISel. Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190961 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/MC/MachineLocation.h | 3 ++- lib/CodeGen/SelectionDAG/FastISel.cpp | 25 ++++++++++--------------- test/DebugInfo/X86/op_deref.ll | 5 +++-- test/DebugInfo/X86/vla.ll | 7 ++++--- 4 files changed, 19 insertions(+), 21 deletions(-) diff --git a/include/llvm/MC/MachineLocation.h b/include/llvm/MC/MachineLocation.h index c4a96606b14..7d9abc3587d 100644 --- a/include/llvm/MC/MachineLocation.h +++ b/include/llvm/MC/MachineLocation.h @@ -44,7 +44,8 @@ public: Offset == Other.Offset; } - // Accessors + // Accessors. + /// \return true iff this is a register-indirect location. bool isIndirect() const { return !IsRegister; } bool isReg() const { return IsRegister; } unsigned getReg() const { return Register; } diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index b25e0317839..5fef4be5dee 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -638,29 +638,24 @@ bool FastISel::SelectCall(const User *I) { (!isa(Address) || !FuncInfo.StaticAllocaMap.count(cast(Address)))) Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address), - false); + false); - if (Op) + if (Op) { if (Op->isReg()) { - // Set the indirect flag if the type and the DIVariable's - // indirect field are in disagreement: Indirectly-addressed - // variables that are nonpointer types should be marked as - // indirect, and VLAs should be marked as indirect eventhough - // they are a pointer type. - bool IsIndirect = DI->getAddress()->getType()->isPointerTy() - ^ DIVar.isIndirect(); Op->setIsDebug(true); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::DBG_VALUE), - IsIndirect, Op->getReg(), Offset, DI->getVariable()); - } else - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0) - .addMetadata(DI->getVariable()); - else + false, Op->getReg(), 0, DI->getVariable()); + } else + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(TargetOpcode::DBG_VALUE)) + .addOperand(*Op).addImm(0) + .addMetadata(DI->getVariable()); + } else { // We can't yet handle anything else here because it would require // generating code, thus altering codegen because of debug info. DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + } return true; } case Intrinsic::dbg_value: { diff --git a/test/DebugInfo/X86/op_deref.ll b/test/DebugInfo/X86/op_deref.ll index a56dd661498..786737a63d4 100644 --- a/test/DebugInfo/X86/op_deref.ll +++ b/test/DebugInfo/X86/op_deref.ll @@ -10,7 +10,8 @@ ; right now, so we check the asm output: ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK ; vla should have a register-indirect address at one point. -; ASM-CHECK: DEBUG_VALUE: vla <- [RCX+0] +; ASM-CHECK: DEBUG_VALUE: vla <- RCX +; ASM-CHECK: DW_OP_breg2 define void @testVLAwithSize(i32 %s) nounwind uwtable ssp { entry: @@ -77,7 +78,7 @@ declare void @llvm.stackrestore(i8*) nounwind !11 = metadata !{i32 1, i32 26, metadata !5, null} !12 = metadata !{i32 3, i32 13, metadata !13, null} !13 = metadata !{i32 786443, metadata !28, metadata !5, i32 2, i32 1, i32 0} ; [ DW_TAG_lexical_block ] -!14 = metadata !{i32 786688, metadata !13, metadata !"vla", metadata !6, i32 3, metadata !15, i32 0, i32 0, i64 2} ; [ DW_TAG_auto_variable ] +!14 = metadata !{i32 786688, metadata !13, metadata !"vla", metadata !6, i32 3, metadata !15, i32 8192, i32 0, i64 2} ; [ DW_TAG_auto_variable ] !15 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !9, metadata !16, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int] !16 = metadata !{metadata !17} !17 = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] diff --git a/test/DebugInfo/X86/vla.ll b/test/DebugInfo/X86/vla.ll index 94e250968bd..ea931e6e385 100644 --- a/test/DebugInfo/X86/vla.ll +++ b/test/DebugInfo/X86/vla.ll @@ -1,6 +1,7 @@ ; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s -; Ensure that we generate a breg+0 location for the variable length array a. -; CHECK: ##DEBUG_VALUE: vla:a <- [RDX+0] +; Ensure that we generate an indirect location for the variable length array a. +; CHECK: ##DEBUG_VALUE: vla:a <- RDX +; CHECK: DW_OP_breg1 ; rdar://problem/13658587 ; ; generated from: @@ -91,7 +92,7 @@ entry: !15 = metadata !{i32 786689, metadata !4, metadata !"n", metadata !5, i32 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [n] [line 1] !16 = metadata !{i32 1, i32 0, metadata !4, null} !17 = metadata !{i32 2, i32 0, metadata !4, null} -!18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 2, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2] +!18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 2, metadata !19, i32 8192, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2] !19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !8, metadata !20, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int] !20 = metadata !{metadata !21} !21 = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] [unbounded] -- 2.34.1