From 0b2081a05acbda2d663703f13b3868f6f1871401 Mon Sep 17 00:00:00 2001 From: Toma Tabacu Date: Thu, 14 Aug 2014 13:10:48 +0000 Subject: [PATCH] [mips] Improve robustness of some tests. Summary: This is done by removing some hardcoded registers like $at or expecting a single digit register to be selected. Contains work done by Matheus Almeida. Reviewers: matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu Differential Revision: http://reviews.llvm.org/D4227 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215640 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/cconv/arguments-float.ll | 16 ++-- test/CodeGen/Mips/cconv/arguments.ll | 6 +- test/CodeGen/Mips/cconv/return-float.ll | 4 +- test/CodeGen/Mips/cconv/return-hard-float.ll | 4 +- test/CodeGen/Mips/cconv/return.ll | 4 +- test/CodeGen/Mips/msa/frameindex.ll | 92 ++++++++++---------- test/CodeGen/Mips/octeon_popcnt.ll | 4 +- 7 files changed, 65 insertions(+), 65 deletions(-) diff --git a/test/CodeGen/Mips/cconv/arguments-float.ll b/test/CodeGen/Mips/cconv/arguments-float.ll index e2119ec0802..0543c61d4d0 100644 --- a/test/CodeGen/Mips/cconv/arguments-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-float.ll @@ -69,26 +69,26 @@ entry: ; O32-DAG: sw [[R4]], 28([[R2]]) ; NEW-DAG: sd $6, 24([[R2]]) -; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp) -; O32-DAG: lw [[R4:\$[0-9]+]], 36($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp) ; O32-DAG: sw [[R3]], 32([[R2]]) ; O32-DAG: sw [[R4]], 36([[R2]]) ; NEW-DAG: sd $7, 32([[R2]]) -; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp) -; O32-DAG: lw [[R4:\$[0-9]+]], 44($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp) ; O32-DAG: sw [[R3]], 40([[R2]]) ; O32-DAG: sw [[R4]], 44([[R2]]) ; NEW-DAG: sd $8, 40([[R2]]) -; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp) -; O32-DAG: lw [[R4:\$[0-9]+]], 52($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp) ; O32-DAG: sw [[R3]], 48([[R2]]) ; O32-DAG: sw [[R4]], 52([[R2]]) ; NEW-DAG: sd $9, 48([[R2]]) -; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp) -; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp) +; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp) +; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp) ; O32-DAG: sw [[R3]], 56([[R2]]) ; O32-DAG: sw [[R4]], 60([[R2]]) ; NEW-DAG: sd $10, 56([[R2]]) diff --git a/test/CodeGen/Mips/cconv/arguments.ll b/test/CodeGen/Mips/cconv/arguments.ll index 8fe29f3c8ce..1ccc39f2dd9 100644 --- a/test/CodeGen/Mips/cconv/arguments.ll +++ b/test/CodeGen/Mips/cconv/arguments.ll @@ -53,7 +53,7 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( +; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( ; The first four arguments are the same in O32/N32/N64 ; ALL-DAG: sb $4, 1([[R1]]) @@ -117,9 +117,9 @@ entry: ; We won't test the way the global address is calculated in this test. This is ; just to get the register number for the other checks. ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) -; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( +; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)( ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) -; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(dwords)( +; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)( ; The first argument is the same in O32/N32/N64. ; ALL-DAG: sb $4, 1([[R1]]) diff --git a/test/CodeGen/Mips/cconv/return-float.ll b/test/CodeGen/Mips/cconv/return-float.ll index 28cf83d3efc..d1a5e4f2fa9 100644 --- a/test/CodeGen/Mips/cconv/return-float.ll +++ b/test/CodeGen/Mips/cconv/return-float.ll @@ -30,7 +30,7 @@ entry: ; O32-DAG: lw $2, %lo(float)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lw $2, %lo(float)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)( ; N64-DAG: lw $2, 0([[R1]]) define double @retdouble() nounwind { @@ -44,5 +44,5 @@ entry: ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double) ; O32-DAG: lw $3, 4([[R2]]) ; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)( ; N64-DAG: ld $2, 0([[R1]]) diff --git a/test/CodeGen/Mips/cconv/return-hard-float.ll b/test/CodeGen/Mips/cconv/return-hard-float.ll index 3eb26fa9d24..123b499185a 100644 --- a/test/CodeGen/Mips/cconv/return-hard-float.ll +++ b/test/CodeGen/Mips/cconv/return-hard-float.ll @@ -33,7 +33,7 @@ entry: ; O32-DAG: lwc1 $f0, %lo(float)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lwc1 $f0, %lo(float)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)( ; N64-DAG: lwc1 $f0, 0([[R1]]) define double @retdouble() nounwind { @@ -45,7 +45,7 @@ entry: ; ALL-LABEL: retdouble: ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)( ; N64-DAG: ldc1 $f0, 0([[R1]]) define { double, double } @retComplexDouble() #0 { diff --git a/test/CodeGen/Mips/cconv/return.ll b/test/CodeGen/Mips/cconv/return.ll index 76ce5e44c4a..63f9b5f45a1 100644 --- a/test/CodeGen/Mips/cconv/return.ll +++ b/test/CodeGen/Mips/cconv/return.ll @@ -33,7 +33,7 @@ entry: ; O32-DAG: lbu $2, %lo(byte)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte) ; N32-DAG: lbu $2, %lo(byte)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)( ; N64-DAG: lbu $2, 0([[R1]]) define i32 @reti32() nounwind { @@ -47,7 +47,7 @@ entry: ; O32-DAG: lw $2, %lo(word)([[R1]]) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word) ; N32-DAG: lw $2, %lo(word)([[R1]]) -; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)($1) +; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)( ; N64-DAG: lw $2, 0([[R1]]) define i64 @reti64() nounwind { diff --git a/test/CodeGen/Mips/msa/frameindex.ll b/test/CodeGen/Mips/msa/frameindex.ll index 07e67bf0428..ebec465a3e3 100644 --- a/test/CodeGen/Mips/msa/frameindex.ll +++ b/test/CodeGen/Mips/msa/frameindex.ll @@ -36,10 +36,10 @@ define void @loadstore_v16i8_just_over_simm10() nounwind { %2 = alloca [497 x i8] ; Push the frame just over 512 bytes %3 = load volatile <16 x i8>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512 ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ret void @@ -53,12 +53,12 @@ define void @loadstore_v16i8_just_under_simm16() nounwind { %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %3 = load volatile <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ret void @@ -72,12 +72,12 @@ define void @loadstore_v16i8_just_over_simm16() nounwind { %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %3 = load volatile <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <16 x i8> %3, <16 x i8>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ret void @@ -107,10 +107,10 @@ define void @loadstore_v8i16_unaligned() nounwind { %5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0 %6 = load volatile <8 x i16>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %6, <8 x i16>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ret void @@ -139,10 +139,10 @@ define void @loadstore_v8i16_just_over_simm10() nounwind { %2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes %3 = load volatile <8 x i16>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024 ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ret void @@ -156,12 +156,12 @@ define void @loadstore_v8i16_just_under_simm16() nounwind { %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %3 = load volatile <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ret void @@ -175,12 +175,12 @@ define void @loadstore_v8i16_just_over_simm16() nounwind { %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %3 = load volatile <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <8 x i16> %3, <8 x i16>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ret void @@ -210,10 +210,10 @@ define void @loadstore_v4i32_unaligned() nounwind { %5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0 %6 = load volatile <4 x i32>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %6, <4 x i32>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ret void @@ -242,10 +242,10 @@ define void @loadstore_v4i32_just_over_simm10() nounwind { %2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes %3 = load volatile <4 x i32>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048 ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ret void @@ -259,12 +259,12 @@ define void @loadstore_v4i32_just_under_simm16() nounwind { %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %3 = load volatile <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ret void @@ -278,12 +278,12 @@ define void @loadstore_v4i32_just_over_simm16() nounwind { %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %3 = load volatile <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <4 x i32> %3, <4 x i32>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ret void @@ -313,10 +313,10 @@ define void @loadstore_v2i64_unaligned() nounwind { %5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0 %6 = load volatile <2 x i64>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %6, <2 x i64>* %5 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1 ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ret void @@ -345,10 +345,10 @@ define void @loadstore_v2i64_just_over_simm10() nounwind { %2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes %3 = load volatile <2 x i64>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096 + ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096 ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ret void @@ -362,12 +362,12 @@ define void @loadstore_v2i64_just_under_simm16() nounwind { %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %3 = load volatile <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ret void @@ -381,12 +381,12 @@ define void @loadstore_v2i64_just_over_simm16() nounwind { %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %3 = load volatile <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) store volatile <2 x i64> %3, <2 x i64>* %1 - ; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 - ; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] + ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768 + ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]] ; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ret void diff --git a/test/CodeGen/Mips/octeon_popcnt.ll b/test/CodeGen/Mips/octeon_popcnt.ll index 52c37f69d02..690b824a4ad 100644 --- a/test/CodeGen/Mips/octeon_popcnt.ll +++ b/test/CodeGen/Mips/octeon_popcnt.ll @@ -6,7 +6,7 @@ define i8 @cnt8(i8 %x) nounwind readnone { ret i8 %cnt ; OCTEON-LABEL: cnt8: ; OCTEON: jr $ra -; OCTEON: pop $2, $1 +; OCTEON: pop $2, [[R1:\$[0-9]+]] ; MIPS64-LABEL: cnt8: ; MIPS64-NOT: pop } @@ -16,7 +16,7 @@ define i16 @cnt16(i16 %x) nounwind readnone { ret i16 %cnt ; OCTEON-LABEL: cnt16: ; OCTEON: jr $ra -; OCTEON: pop $2, $1 +; OCTEON: pop $2, [[R1:\$[0-9]+]] ; MIPS64-LABEL: cnt16: ; MIPS64-NOT: pop } -- 2.34.1