From 0b8594268feb1c804370541c7853e658caee0ae5 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Wed, 26 Jun 2013 13:49:15 +0000 Subject: [PATCH] [PowerPC] Support symbolic u16imm operands Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 5 ++++- lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 6 +++--- lib/Target/PowerPC/PPCCodeEmitter.cpp | 6 +++--- lib/Target/PowerPC/PPCInstr64Bit.td | 3 ++- lib/Target/PowerPC/PPCInstrInfo.td | 3 ++- test/MC/PowerPC/ppc64-fixups.s | 10 ++++++++++ 6 files changed, 24 insertions(+), 9 deletions(-) diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index eee1f45ff5d..a6763026686 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -205,7 +205,10 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { - O << (unsigned short)MI->getOperand(OpNo).getImm(); + if (MI->getOperand(OpNo).isImm()) + O << (unsigned short)MI->getOperand(OpNo).getImm(); + else + printOperand(MI, OpNo, O); } void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo, diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 1c6adac33e3..06574753f94 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -52,7 +52,7 @@ public: SmallVectorImpl &Fixups) const; unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups) const; - unsigned getS16ImmEncoding(const MCInst &MI, unsigned OpNo, + unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups) const; unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups) const; @@ -162,12 +162,12 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, return 0; } -unsigned PPCMCCodeEmitter::getS16ImmEncoding(const MCInst &MI, unsigned OpNo, +unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); - // Add a fixup for the branch target. + // Add a fixup for the immediate field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_half16)); return 0; diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index f006b49d7c4..382d709afa8 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -67,7 +67,7 @@ namespace { unsigned OpNo) const; unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getS16ImmEncoding(const MachineInstr &MI, unsigned OpNo) const; + unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const; unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const; @@ -209,8 +209,8 @@ unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI, llvm_unreachable("Absolute branch relocations unsupported on the old JIT."); } -unsigned PPCCodeEmitter::getS16ImmEncoding(const MachineInstr &MI, - unsigned OpNo) const { +unsigned PPCCodeEmitter::getImm16Encoding(const MachineInstr &MI, + unsigned OpNo) const { const MachineOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index d612fd96992..f63ca241cfc 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -17,11 +17,12 @@ // def s16imm64 : Operand { let PrintMethod = "printS16ImmOperand"; - let EncoderMethod = "getS16ImmEncoding"; + let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def u16imm64 : Operand { let PrintMethod = "printU16ImmOperand"; + let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCU16ImmAsmOperand; } def tocentry : Operand { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index a9cfd5ef872..a9706967331 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -434,7 +434,7 @@ def PPCS16ImmAsmOperand : AsmOperandClass { } def s16imm : Operand { let PrintMethod = "printS16ImmOperand"; - let EncoderMethod = "getS16ImmEncoding"; + let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCS16ImmAsmOperand; } def PPCU16ImmAsmOperand : AsmOperandClass { @@ -443,6 +443,7 @@ def PPCU16ImmAsmOperand : AsmOperandClass { } def u16imm : Operand { let PrintMethod = "printU16ImmOperand"; + let EncoderMethod = "getImm16Encoding"; let ParserMatchClass = PPCU16ImmAsmOperand; } def PPCDirectBrAsmOperand : AsmOperandClass { diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s index d7dfc50bd8a..18811fa4118 100644 --- a/test/MC/PowerPC/ppc64-fixups.s +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -133,6 +133,16 @@ base: # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE li 3, target-base@ha +# CHECK: ori 3, 3, target@l # encoding: [0x60,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0 + ori 3, 3, target@l + +# CHECK: oris 3, 3, target@h # encoding: [0x64,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16 +# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0 + oris 3, 3, target@h + # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] # CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0 -- 2.34.1