From 0bf9d0684ae3052da72e56d49d8465bb26cc12ba Mon Sep 17 00:00:00 2001
From: root <root@xxx-desktop.(none)>
Date: Mon, 6 Jun 2011 04:08:43 +0800
Subject: [PATCH] add a function that spi driver codecs can run in sram

---
 arch/arm/mach-rk29/Kconfig                   |   3 +
 arch/arm/mach-rk29/Makefile                  |   1 +
 arch/arm/mach-rk29/include/mach/rk29_iomap.h |   2 +
 arch/arm/mach-rk29/io.c                      |   2 +
 arch/arm/mach-rk29/pm.c                      |  21 ++-
 arch/arm/mach-rk29/spi_sram.c                | 131 +++++++++++++++++++
 6 files changed, 159 insertions(+), 1 deletion(-)
 mode change 100755 => 100644 arch/arm/mach-rk29/Kconfig
 mode change 100644 => 100755 arch/arm/mach-rk29/include/mach/rk29_iomap.h
 mode change 100755 => 100644 arch/arm/mach-rk29/pm.c
 create mode 100644 arch/arm/mach-rk29/spi_sram.c

diff --git a/arch/arm/mach-rk29/Kconfig b/arch/arm/mach-rk29/Kconfig
old mode 100755
new mode 100644
index f52d25e83502..91433adc823a
--- a/arch/arm/mach-rk29/Kconfig
+++ b/arch/arm/mach-rk29/Kconfig
@@ -179,5 +179,8 @@ config RK29_LAST_LOG
 	default y
 	help
 	  It is only intended for debugging.
+config RK29_SRAM_SPI
+	tristate "Support spi driver codec run in sram"
+	default n
 
 endif
diff --git a/arch/arm/mach-rk29/Makefile b/arch/arm/mach-rk29/Makefile
index e2c0ed70b24f..fc77b8e9baf5 100644
--- a/arch/arm/mach-rk29/Makefile
+++ b/arch/arm/mach-rk29/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_GADGET) += usb_detect.o
 obj-$(CONFIG_PM) += pm.o
 obj-$(CONFIG_CPU_FREQ) += cpufreq.o
 obj-$(CONFIG_RK29_VPU) += vpu.o vpu_mem.o
+obj-$(CONFIG_RK29_SRAM_SPI) += spi_sram.o
 obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
 obj-$(CONFIG_MACH_RK29SDK_DDR3) += board-rk29-ddr3sdk.o board-rk29sdk-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
 obj-$(CONFIG_MACH_RK29WINACCORD) += board-rk29-winaccord.o board-rk29sdk-key.o
diff --git a/arch/arm/mach-rk29/include/mach/rk29_iomap.h b/arch/arm/mach-rk29/include/mach/rk29_iomap.h
old mode 100644
new mode 100755
index f089fcbec7a5..200113c5e195
--- a/arch/arm/mach-rk29/include/mach/rk29_iomap.h
+++ b/arch/arm/mach-rk29/include/mach/rk29_iomap.h
@@ -169,8 +169,10 @@
 #define RK29_ADC_PHYS				0x2006C000
 #define RK29_ADC_SIZE				SZ_16K
 #define RK29_SPI0_PHYS				0x20070000
+#define RK29_SPI0_BASE				(RK29_ADDR_BASE1+0x70000)
 #define RK29_SPI0_SIZE				SZ_16K
 #define RK29_SPI1_PHYS				0x20074000
+#define RK29_SPI1_BASE				(RK29_ADDR_BASE1+0x74000)
 #define RK29_SPI1_SIZE				SZ_16K
 #define RK29_DMAC1_PHYS				0x20078000
 #define RK29_DMAC1_SIZE				SZ_16K
diff --git a/arch/arm/mach-rk29/io.c b/arch/arm/mach-rk29/io.c
index 9815a2734756..b2e930417e95 100644
--- a/arch/arm/mach-rk29/io.c
+++ b/arch/arm/mach-rk29/io.c
@@ -50,6 +50,8 @@ static struct map_desc rk29_io_desc[] __initdata = {
 	RK29_DEVICE(GPIO5),
 	RK29_DEVICE(GPIO6),
 	RK29_DEVICE(NANDC),
+	RK29_DEVICE(SPI0),
+	RK29_DEVICE(SPI1),
 };
 
 void __init rk29_map_common_io(void)
diff --git a/arch/arm/mach-rk29/pm.c b/arch/arm/mach-rk29/pm.c
old mode 100755
new mode 100644
index 0fa338fb037e..9aab0ef6cd38
--- a/arch/arm/mach-rk29/pm.c
+++ b/arch/arm/mach-rk29/pm.c
@@ -29,6 +29,15 @@
 
 #include <mach/iomux.h>
 
+#if defined(CONFIG_RK29_SRAM_SPI)
+void sram_spi_pread(void);
+void __sramfunc rk29_spi_ctr_vol_sleep(void);
+void __sramfunc rk29_spi_ctr_vol_resume(void);
+#else
+#define sram_spi_pread()
+#define rk29_spi_ctr_vol_sleep()
+#define rk29_spi_ctr_vol_resume()
+#endif
 
 #define grf_readl(offset) readl(RK29_GRF_BASE + offset)
 #define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
@@ -279,6 +288,10 @@ static void __sramfunc rk29_sram_suspend(void)
 #ifdef CONFIG_RK29_PWM_REGULATOR
 	rk29_set_core_voltage(1000000);
 #endif
+#if defined(CONFIG_RK29_SRAM_SPI)
+	rk29_spi_ctr_vol_sleep();
+#endif
+
 	printch('7');
 	clksel0 = cru_readl(CRU_CLKSEL0_CON);
 	/* set arm clk 24MHz/32 = 750KHz */
@@ -296,6 +309,10 @@ static void __sramfunc rk29_sram_suspend(void)
 #ifdef CONFIG_RK29_PWM_REGULATOR
 	rk29_set_core_voltage(0);
 #endif
+#if defined(CONFIG_RK29_SRAM_SPI)
+	rk29_spi_ctr_vol_resume();
+#endif
+
 	printch('6');
 
 	ddr_resume();
@@ -469,7 +486,9 @@ static int rk29_pm_enter(suspend_state_t state)
 	delay_500ns();
 	/* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
 	cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
-
+#if defined(CONFIG_RK29_SRAM_SPI)
+	sram_spi_pread();
+#endif
 	printch('4');
 	
 	rk29_suspend();
diff --git a/arch/arm/mach-rk29/spi_sram.c b/arch/arm/mach-rk29/spi_sram.c
new file mode 100644
index 000000000000..2c7eb3358015
--- /dev/null
+++ b/arch/arm/mach-rk29/spi_sram.c
@@ -0,0 +1,131 @@
+
+#include <mach/spi_sram.h>
+
+unsigned __sramdata  int spibase;
+u32 __sramdata spi_base[2]={RK29_SPI0_BASE,RK29_SPI1_BASE};
+u32 __sramdata spi_data[6]={};
+
+//chcs : &0xf0->ch(spi1spi0), &ox0f->cs(cs1cs0)
+
+void __sramfunc delay_test(int delay_time)
+{
+    int n = 100 * delay_time;
+    while(n--)
+    {
+        __asm__ __volatile__("");
+    }
+}
+
+void  __sramfunc spi_reg_init(unsigned char size,unsigned char ch,unsigned char cs){
+	unsigned int ret=0;
+	
+	spibase=spi_base[ch];
+	ret=readl(spibase + SPIM_ENR);
+	 writel(ret&~(0x1<<0), spibase + SPIM_ENR);  //disable SPI reg
+
+	 ret = readl(spibase + SPIM_SER);
+	writel(ret&~(0xffffffff)|(0x1<<cs), spibase + SPIM_SER);    //cs0\1  
+	
+	ret = readl(spibase + SPIM_CTRLR0);	
+	spi_data[5]=ret&~(1<<18)&~(1<<13)&~(1<<8)&~(0x3<<1)|(1<<11);
+	writel(spi_data[5]|size,spibase + SPIM_CTRLR0);             //  16\8\4 wei
+	                                          
+	ret=readl(spibase + SPIM_BAUDR);
+	writel(ret&(~0xffff)|0x2,spibase + SPIM_BAUDR);          //sout clk
+
+	ret=readl(spibase + SPIM_ENR);
+	writel(ret|0x1, spibase + SPIM_ENR);                         //enable spi
+
+}
+void  __sramfunc spi_deinit(void){
+	
+	writel(spi_data[0],RK29_GRF_BASE + 0x5c);	
+	writel(spi_data[1],RK29_GRF_BASE +0x50);
+	writel(0, spibase + SPIM_ENR);  
+	writel(spi_data[2], RK29_CRU_BASE + CRU_CLKSEL6_CON);
+	writel(spi_data[3],RK29_CRU_BASE + CRU_CLKGATE2_CON); 
+	writel(spi_data[4],RK29_CRU_BASE + CRU_CLKGATE1_CON);
+	
+}
+ void __sramfunc spi_init( unsigned char ch,unsigned char cs){
+	unsigned int ret=0;
+	ret=readl(RK29_CRU_BASE + CRU_CLKGATE1_CON);
+	spi_data[4]=ret;
+	writel(ret&~(1<<3)&~(1<<2)&~(1<<1)&~(1<<0),RK29_CRU_BASE + CRU_CLKGATE1_CON);
+	spi_data[3]=readl(RK29_CRU_BASE + CRU_CLKGATE2_CON);
+	spi_data[0]=readl(RK29_GRF_BASE +0x5c);
+	spi_data[2]=readl(RK29_CRU_BASE + CRU_CLKSEL6_CON);
+	spi_data[1]=readl(RK29_GRF_BASE +0x50);
+	writel(spi_data[3]&~(1<<(15+ch)),RK29_CRU_BASE + CRU_CLKGATE2_CON);   //spi0\1  clk enable
+	writel(spi_data[1]&~(1<<(8-2*ch))|(1<<(9-2*ch)),RK29_GRF_BASE +0x50);    //sp0\1 cs1  iomux
+	writel(spi_data[0]&~(1<<(3+8*ch))|(1<<(2+8*ch)),RK29_GRF_BASE +0x5c);   //spi0\1 cs0 iomux
+	if(ch!=0){
+		writel(spi_data[2]&~(0x7f<<11)|(0x0b<<11),RK29_CRU_BASE + CRU_CLKSEL6_CON);     //spi1 clk speed
+		writel(spi_data[0]&~(1<<15)&~(1<<13)&~(1<<9)|(1<<14)|(1<<12)|(1<<8),RK29_GRF_BASE +0x5c);   //spi1 clk\txd\rxd iomux 
+	}
+	else{
+		writel(spi_data[2]&~(0x7f<<2)|(0x0b<<2),RK29_CRU_BASE + CRU_CLKSEL6_CON);     //spi0 clk speed
+		writel(spi_data[0]&~(1<<7)&~(1<<5)&~(1<<1)|(1<<6)|(1<<4)|(1<<0),RK29_GRF_BASE +0x5c);   //spi0 clk\txd\rxd iomux
+	}
+}
+
+static void __sramfunc spi_write(unsigned int add,unsigned int data){
+  	unsigned int ret=0;
+	spi_reg_init(2,1,1);
+	writel(add, spibase + SPIM_TXDR);
+	delay_test(100);
+	writel(data, spibase + SPIM_TXDR);
+	delay_test(100);
+	ret = readl(spibase + SPIM_SER);
+	writel(ret&~(0xffffffff), spibase + SPIM_SER);    
+
+}
+ static unsigned int __sramfunc spi_read(unsigned int add,unsigned int data){
+  	unsigned int ret=0,ret1=0;
+	spi_reg_init(2,1,1);
+	writel(add, spibase + SPIM_TXDR);
+	delay_test(100);
+	writel(data, spibase + SPIM_TXDR);
+	delay_test(100);
+	ret=readl(spibase + SPIM_RXDR); 
+	//printhex(ret);
+	//printch('\n');
+	ret1=readl(spibase + SPIM_RXDR); 
+	//printhex(ret1);
+	//printch('\n');
+	return ret1;
+	ret = readl(spibase + SPIM_SER);
+	writel(ret&~(0xffffffff), spibase + SPIM_SER);  
+	
+}
+void __sramfunc rk29_wm831x_sleep_test(void){
+     
+	unsigned int data2 = 0xc003, data1 = 0x4128,ret = 0; 
+	unsigned int addw2 = 0x4003,addw1 = 0x405d;
+	unsigned int addr2= 0xc003,addr1= 0xc05d;
+	unsigned int size=2,ch=1,cs=1;    //DATA SIZE IS 2^(size+2)  (16wei)   ch0\1 is spi0\1     
+	//printch('\n');
+	spi_init(ch,cs);    //iomux  clk
+	spi_reg_init(2,1,1);  //spi reg     size, ch,cs
+	spi_write(addw1,data1);
+	ret=spi_read(addr1,data1);
+	spi_write(addw2,data2);	
+	spi_deinit();
+		
+} 
+void __sramfunc rk29_wm831x_resume_test(void){
+     
+	unsigned int data4 = 0x8003, data3 = 0x4140,ret = 0; 
+	unsigned int addw4 = 0x4003,addw3 = 0x405d;
+	unsigned int addr4= 0xc003,addr3= 0xc05d;
+	unsigned int size=2,ch=1,cs=1;
+	//printch('\n');
+	spi_init(ch,cs);          // clk iomux
+	spi_reg_init(2,1,1);         //spi reg       size,ch,cs
+	spi_write(addw3,data3);  
+	ret=spi_read(addr3,data3);
+	spi_write(addw4,data4);	
+	spi_deinit();   
+}
+
+
-- 
2.34.1