From 0c1b9ec2dc1f5899a5c711d6ee4d8d66f1174e39 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 22 Jan 2014 03:38:55 +0000 Subject: [PATCH] Reformat a loop for basic hygeine. Self review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199788 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineScheduler.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index 4812b30526a..2de3d20e597 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -2527,17 +2527,17 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) { const TargetMachine &TM = Context->MF->getTarget(); + const TargetLowering *TLI = TM.getTargetLowering(); // Avoid setting up the register pressure tracker for small regions to save // compile time. As a rough heuristic, only track pressure when the number of // schedulable instructions exceeds half the integer register file. RegionPolicy.ShouldTrackPressure = true; - unsigned LegalIntVT = MVT::i32; - for (; LegalIntVT > (unsigned)MVT::i1; --LegalIntVT) { - if (TM.getTargetLowering()->isTypeLegal((MVT::SimpleValueType)LegalIntVT)) { + for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) { + MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT; + if (TLI->isTypeLegal(LegalIntVT)) { unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs( - TM.getTargetLowering()->getRegClassFor( - (MVT::SimpleValueType)LegalIntVT)); + TLI->getRegClassFor(LegalIntVT)); RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2); } } -- 2.34.1