From 0d47c1d85b137abcce62e9a236f5c39b7107e80a Mon Sep 17 00:00:00 2001 From: Wu Liang feng Date: Wed, 6 Jul 2016 11:22:49 +0800 Subject: [PATCH] arm64: dts: rockchip: add u2phy0 and u2phy0_otg node for rk3399 RK3399 SoC usb2 PHY comprises with one host-port and one otg-port, we support otg-port for the time being. Change-Id: I7d6a464372603e54c3a06d994e18d80eb84fa5a5 Signed-off-by: Wu Liang feng --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 0667430c6166..ab5c03ba4572 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1175,8 +1175,30 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3399-grf", "syscon"; + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; }; watchdog@ff840000 { -- 2.34.1