From 0dec0e1ea5a7df2aca129fdbe8fb1db87938c593 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Fri, 17 Jul 2015 23:18:26 +0000 Subject: [PATCH] ARM: Add scheduling information for LDRLIT instructions to swift scheduling model These pseudo instructions are only lowered after register allocation and are therefore still present when the machine scheduler runs. Add a run: line to a testcase that uses the uncommon flags necessary to actually produce a LDRLIT instruction on swift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242587 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMScheduleSwift.td | 7 +++++++ test/CodeGen/Thumb2/pic-load.ll | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index b03d5ff44c6..ff82ca41908 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1558,6 +1558,13 @@ let SchedModel = SwiftModel in { (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", "PUSH", "tPUSH")>; + // LDRLIT pseudo instructions, they expand to LDR + PICADD + def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU], + (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>; + // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR + def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle], + (instregex "LDRLIT_ga_pcrel_ldr")>; + // 4.2.26 Branch def : WriteRes { let Latency = 0; } def : WriteRes { let Latency = 2; } diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll index 53d456c5345..cfdad03dcd5 100644 --- a/test/CodeGen/Thumb2/pic-load.ll +++ b/test/CodeGen/Thumb2/pic-load.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=PIC +; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -mcpu=swift -mattr=+no-movt | FileCheck %s --check-prefix=CHECK --check-prefix=PIC-NOMOVT %struct.anon = type { void ()* } %struct.one_atexit_routine = type { %struct.anon, i32, i8* } @@ -8,7 +9,14 @@ define hidden i32 @atexit(void ()* %func) nounwind { entry: ; CHECK-LABEL: atexit: -; CHECK: add r0, pc +; CHECK-PIC: add r0, pc +; CHECK-NOMOVT: ldr r[[REGNUM:[0-9]+]], LCPI0_0 +; CHECK-NOMOVT: LPC0_0: +; CHECK-NOMOVT: add r[[REGNUM]], pc +; CHECK-NOMOVT: ldr r1, [r[[REGNUM]] +; CHECK-NOMOVT: blx _atexit_common +; CHECK-NOMOVT: LCPI0_0: +; CHECK-NOMOVT: .long L___dso_handle$non_lazy_ptr-(LPC0_0+4) %r = alloca %struct.one_atexit_routine, align 4 ; <%struct.one_atexit_routine*> [#uses=3] %0 = getelementptr %struct.one_atexit_routine, %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0 ; [#uses=1] store void ()* %func, void ()** %0, align 4 -- 2.34.1