From 0e4dd01ffc44222d68c3c5e2c1a45c8c1a1d20ae Mon Sep 17 00:00:00 2001
From: Andrew Lenharth <andrewl@lenharth.org>
Date: Tue, 13 Jun 2006 18:27:39 +0000
Subject: [PATCH] It really helps to be returning to the correct place

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28769 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 32 ++++----------------------
 lib/Target/Alpha/AlphaISelLowering.cpp | 15 +++++++-----
 lib/Target/Alpha/AlphaISelLowering.h   |  3 +++
 3 files changed, 17 insertions(+), 33 deletions(-)

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 0073beaa54c..885fcf445c2 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -124,7 +124,7 @@ namespace {
     
 private:
     SDOperand getGlobalBaseReg();
-    SDOperand getRASaveReg();
+    SDOperand getGlobalRetAddr();
     SDOperand SelectCALL(SDOperand Op);
 
   };
@@ -141,7 +141,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
 
 /// getRASaveReg - Grab the return address
 ///
-SDOperand AlphaDAGToDAGISel::getRASaveReg() {
+SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
                                 AlphaLowering.getVRegRA(), 
                                 MVT::i64);
@@ -197,6 +197,9 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   case AlphaISD::GlobalBaseReg: 
     Result = getGlobalBaseReg();
     return;
+  case AlphaISD::GlobalRetAddr:
+    Result = getGlobalRetAddr();
+    return;
   
   case AlphaISD::DivCall: {
     SDOperand Chain = CurDAG->getEntryNode();
@@ -226,30 +229,6 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     return;
   }
 
-  case ISD::RET: {
-    SDOperand Chain;
-    Select(Chain, N->getOperand(0));     // Token chain.
-    SDOperand InFlag(0,0);
-
-    if (N->getNumOperands() == 3) {
-      SDOperand Val;
-      Select(Val, N->getOperand(1));
-      if (N->getOperand(1).getValueType() == MVT::i64) {
-        Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
-        InFlag = Chain.getValue(1);
-      } else if (N->getOperand(1).getValueType() == MVT::f64 ||
-                 N->getOperand(1).getValueType() == MVT::f32) {
-        Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
-        InFlag = Chain.getValue(1);
-      }
-    }
-    Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
-    InFlag = Chain.getValue(1);
-    
-    // Finally, select this to a ret instruction.
-    Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
-    return;
-  }
   case ISD::Constant: {
     uint64_t uval = cast<ConstantSDNode>(N)->getValue();
     
@@ -469,7 +448,6 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
        assert(0 && "Unknown operand"); 
    }
 
-
    // Finally, once everything is in registers to pass to the call, emit the
    // call itself.
    if (Addr.getOpcode() == AlphaISD::GPRelLo) {
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 3a5c7d92e8d..fda3096e3cf 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -154,6 +154,7 @@ const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
   case AlphaISD::RelLit: return "Alpha::RelLit";
   case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
+  case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
   case AlphaISD::CALL:   return "Alpha::CALL";
   case AlphaISD::DivCall: return "Alpha::DivCall";
   case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
@@ -268,14 +269,17 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
 }
 
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
-  SDOperand Copy;
+static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
+  SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 
+				    DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64),
+				    SDOperand());
   switch (Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
     abort();
   case 1: 
-    return SDOperand(); // ret void is legal
+    break;
+    //return SDOperand(); // ret void is legal
   case 3: {
     MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
     unsigned ArgReg;
@@ -285,8 +289,7 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
       assert(MVT::isFloatingPoint(ArgVT));
       ArgReg = Alpha::F0;
     }
-    Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
-                            SDOperand());
+    Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
     if(DAG.getMachineFunction().liveout_empty())
       DAG.getMachineFunction().addLiveOut(ArgReg);
     break;
@@ -384,7 +387,7 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
 							   VarArgsBase,
 							   VarArgsOffset,
 							   GP, RA);
-  case ISD::RET: return LowerRET(Op,DAG);
+  case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
   case ISD::SINT_TO_FP: {
     assert(MVT::i64 == Op.getOperand(0).getValueType() && 
            "Unhandled SINT_TO_FP type in custom expander!");
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index 28bbfc50a9b..f7906d66055 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -37,6 +37,9 @@ namespace llvm {
 
       /// GlobalBaseReg - used to restore the GOT ptr
       GlobalBaseReg,
+
+      /// GlobalRetAddr - used to restore the return address
+      GlobalRetAddr,
       
       /// CALL - Normal call.
       CALL,
-- 
2.34.1