From 0f1294525b11a9cb4115bef712cf70fce93b315f Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Fri, 31 Mar 2017 11:18:39 +0800 Subject: [PATCH] clk: rockchip: rk3399: Don't allow VPLL as aclk_cci clock source vpll is just for dclk_vop. Don't allow are other child under the VPLL. Change-Id: I755348b4104b532c693c6874127a25721187a4ad Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index e8831e4e8c07..f4344548d738 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -151,7 +151,7 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_p) = { "dummy_vpll", "cpll", "gpll" }; PNAME(mux_aclk_cci_p) = { "dummy_cpll", "gpll_aclk_cci_src", "npll_aclk_cci_src", - "vpll_aclk_cci_src" }; + "dummy_vpll" }; PNAME(mux_cci_trace_p) = { "dummy_cpll", "gpll_cci_trace" }; PNAME(mux_cs_p) = { "dummy_cpll", "gpll_cs", @@ -205,7 +205,7 @@ PNAME(mux_aclk_gmac_p) = { "dummy_cpll", PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", - "vpll_aclk_cci_src" }; + "dummy_vpll" }; PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" }; PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", -- 2.34.1