From 0f27fc34f7e6f12069527b209127424416d941f3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 13 Sep 2006 04:45:25 +0000 Subject: [PATCH] Fix a regression in the 32-bit port from the 64-bit port landing. We now compile CodeGen/X86/lea-2.ll into: _test: movl 4(%esp), %eax movl 8(%esp), %ecx leal -5(%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal (,%eax,4), %eax addl 8(%esp), %eax addl $4294967291, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelDAGToDAG.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 20e7edc668f..9d655b0677b 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -498,7 +498,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, // RIP relative addressing: %rip + 32-bit displacement! if (AM.isRIPRel) { if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) { - uint64_t Val = cast(N)->getValue(); + int64_t Val = cast(N)->getSignExtended(); if (isInt32(AM.Disp + Val)) { AM.Disp += Val; return false; @@ -513,7 +513,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM, switch (N.getOpcode()) { default: break; case ISD::Constant: { - uint64_t Val = cast(N)->getValue(); + int64_t Val = cast(N)->getSignExtended(); if (isInt32(AM.Disp + Val)) { AM.Disp += Val; return false; -- 2.34.1