From 0fee6d970351d82e6636d0ac2dcf424a8ac99235 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 6 Jan 2014 06:51:58 +0000 Subject: [PATCH] Remove SegOvrBits from X86 TSFlags since they weren't being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198588 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 9 +--- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 36 ++++++---------- lib/Target/X86/X86CodeEmitter.cpp | 36 ++++++---------- lib/Target/X86/X86InstrFormats.td | 42 +++++++++---------- 4 files changed, 46 insertions(+), 77 deletions(-) diff --git a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index 3de5d8255d3..888dc8bf5ef 100644 --- a/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -417,16 +417,9 @@ namespace X86II { LOCKShift = FPTypeShift + 3, LOCK = 1 << LOCKShift, - // Segment override prefixes. Currently we just need ability to address - // stuff in gs and fs segments. - SegOvrShift = LOCKShift + 1, - SegOvrMask = 3 << SegOvrShift, - FS = 1 << SegOvrShift, - GS = 2 << SegOvrShift, - // Execution domain for SSE instructions in bits 23, 24. // 0 in bits 23-24 means normal, non-SSE instruction. - SSEDomainShift = SegOvrShift + 2, + SSEDomainShift = LOCKShift + 1, OpcodeShift = SSEDomainShift + 2, diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index a9f023616e2..e44574c31e2 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1123,29 +1123,19 @@ void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, raw_ostream &OS) const { - switch (TSFlags & X86II::SegOvrMask) { - default: llvm_unreachable("Invalid segment!"); - case 0: - // No segment override, check for explicit one on memory operand. - if (MemOperand != -1) { // If the instruction has a memory operand. - switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { - default: llvm_unreachable("Unknown segment register!"); - case 0: break; - case X86::CS: EmitByte(0x2E, CurByte, OS); break; - case X86::SS: EmitByte(0x36, CurByte, OS); break; - case X86::DS: EmitByte(0x3E, CurByte, OS); break; - case X86::ES: EmitByte(0x26, CurByte, OS); break; - case X86::FS: EmitByte(0x64, CurByte, OS); break; - case X86::GS: EmitByte(0x65, CurByte, OS); break; - } - } - break; - case X86II::FS: - EmitByte(0x64, CurByte, OS); - break; - case X86II::GS: - EmitByte(0x65, CurByte, OS); - break; + if (MemOperand < 0) + return; // No memory operand + + // Check for explicit segment override on memory operand. + switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { + default: llvm_unreachable("Unknown segment register!"); + case 0: break; + case X86::CS: EmitByte(0x2E, CurByte, OS); break; + case X86::SS: EmitByte(0x36, CurByte, OS); break; + case X86::DS: EmitByte(0x3E, CurByte, OS); break; + case X86::ES: EmitByte(0x26, CurByte, OS); break; + case X86::FS: EmitByte(0x64, CurByte, OS); break; + case X86::GS: EmitByte(0x65, CurByte, OS); break; } } diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 0d3989d8510..072996679bc 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -774,29 +774,19 @@ template void Emitter::emitSegmentOverridePrefix(uint64_t TSFlags, int MemOperand, const MachineInstr &MI) const { - switch (TSFlags & X86II::SegOvrMask) { - default: llvm_unreachable("Invalid segment!"); - case 0: - // No segment override, check for explicit one on memory operand. - if (MemOperand != -1) { // If the instruction has a memory operand. - switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { - default: llvm_unreachable("Unknown segment register!"); - case 0: break; - case X86::CS: MCE.emitByte(0x2E); break; - case X86::SS: MCE.emitByte(0x36); break; - case X86::DS: MCE.emitByte(0x3E); break; - case X86::ES: MCE.emitByte(0x26); break; - case X86::FS: MCE.emitByte(0x64); break; - case X86::GS: MCE.emitByte(0x65); break; - } - } - break; - case X86II::FS: - MCE.emitByte(0x64); - break; - case X86II::GS: - MCE.emitByte(0x65); - break; + if (MemOperand < 0) + return; // No memory operand + + // Check for explicit segment override on memory operand. + switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { + default: llvm_unreachable("Unknown segment register!"); + case 0: break; + case X86::CS: MCE.emitByte(0x2E); break; + case X86::SS: MCE.emitByte(0x36); break; + case X86::DS: MCE.emitByte(0x3E); break; + case X86::ES: MCE.emitByte(0x26); break; + case X86::FS: MCE.emitByte(0x64); break; + case X86::GS: MCE.emitByte(0x65); break; } } diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index ea146b23ed3..105fa0c9a98 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -116,8 +116,6 @@ class OpSize16 { bit hasOpSize16Prefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } -class SegFS { bits<2> SegOvrBits = 1; } -class SegGS { bits<2> SegOvrBits = 2; } class TB { bits<5> Prefix = 1; } class REP { bits<5> Prefix = 2; } class D8 { bits<5> Prefix = 3; } @@ -199,7 +197,6 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? FPFormat FPForm = NotFP; // What flavor of FP instruction is this? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? - bits<2> SegOvrBits = 0; // Segment override prefix. Domain ExeDomain = d; bit hasVEXPrefix = 0; // Does this inst require a VEX prefix? bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? @@ -231,26 +228,25 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, let TSFlags{17-15} = ImmT.Value; let TSFlags{20-18} = FPForm.Value; let TSFlags{21} = hasLockPrefix; - let TSFlags{23-22} = SegOvrBits; - let TSFlags{25-24} = ExeDomain.Value; - let TSFlags{33-26} = Opcode; - let TSFlags{34} = hasVEXPrefix; - let TSFlags{35} = hasVEX_WPrefix; - let TSFlags{36} = hasVEX_4VPrefix; - let TSFlags{37} = hasVEX_4VOp3Prefix; - let TSFlags{38} = hasVEX_i8ImmReg; - let TSFlags{39} = hasVEX_L; - let TSFlags{40} = ignoresVEX_L; - let TSFlags{41} = hasEVEXPrefix; - let TSFlags{42} = hasEVEX_K; - let TSFlags{43} = hasEVEX_Z; - let TSFlags{44} = hasEVEX_L2; - let TSFlags{45} = hasEVEX_B; - let TSFlags{47-46} = EVEX_CD8E; - let TSFlags{50-48} = EVEX_CD8V; - let TSFlags{51} = has3DNow0F0FOpcode; - let TSFlags{52} = hasMemOp4Prefix; - let TSFlags{53} = hasXOP_Prefix; + let TSFlags{23-22} = ExeDomain.Value; + let TSFlags{31-24} = Opcode; + let TSFlags{32} = hasVEXPrefix; + let TSFlags{33} = hasVEX_WPrefix; + let TSFlags{34} = hasVEX_4VPrefix; + let TSFlags{35} = hasVEX_4VOp3Prefix; + let TSFlags{36} = hasVEX_i8ImmReg; + let TSFlags{37} = hasVEX_L; + let TSFlags{38} = ignoresVEX_L; + let TSFlags{39} = hasEVEXPrefix; + let TSFlags{40} = hasEVEX_K; + let TSFlags{41} = hasEVEX_Z; + let TSFlags{42} = hasEVEX_L2; + let TSFlags{43} = hasEVEX_B; + let TSFlags{45-44} = EVEX_CD8E; + let TSFlags{48-46} = EVEX_CD8V; + let TSFlags{49} = has3DNow0F0FOpcode; + let TSFlags{50} = hasMemOp4Prefix; + let TSFlags{51} = hasXOP_Prefix; } class PseudoI pattern> -- 2.34.1