From 109f9e6f715dc178adf1f39e301e919e33733081 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 24 Oct 2015 12:46:49 +0000 Subject: [PATCH] [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251187 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenSchedule.cpp | 91 ++++++++++++++---------------- utils/TableGen/CodeGenSchedule.h | 39 ++++++------- 2 files changed, 61 insertions(+), 69 deletions(-) diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp index bc27481869f..c98f6234534 100644 --- a/utils/TableGen/CodeGenSchedule.cpp +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -24,15 +24,9 @@ using namespace llvm; #define DEBUG_TYPE "subtarget-emitter" #ifndef NDEBUG -static void dumpIdxVec(const IdxVec &V) { - for (unsigned i = 0, e = V.size(); i < e; ++i) { - dbgs() << V[i] << ", "; - } -} -static void dumpIdxVec(const SmallVectorImpl &V) { - for (unsigned i = 0, e = V.size(); i < e; ++i) { - dbgs() << V[i] << ", "; - } +static void dumpIdxVec(ArrayRef V) { + for (unsigned Idx : V) + dbgs() << Idx << ", "; } #endif @@ -326,9 +320,9 @@ void CodeGenSchedModels::collectSchedRW() { } /// Compute a SchedWrite name from a sequence of writes. -std::string CodeGenSchedModels::genRWName(const IdxVec& Seq, bool IsRead) { +std::string CodeGenSchedModels::genRWName(ArrayRef Seq, bool IsRead) { std::string Name("("); - for (IdxIter I = Seq.begin(), E = Seq.end(); I != E; ++I) { + for (auto I = Seq.begin(), E = Seq.end(); I != E; ++I) { if (I != Seq.begin()) Name += '_'; Name += getSchedRW(*I, IsRead).Name; @@ -457,13 +451,13 @@ void CodeGenSchedModels::expandRWSeqForProc( } // Find the existing SchedWrite that models this sequence of writes. -unsigned CodeGenSchedModels::findRWForSequence(const IdxVec &Seq, +unsigned CodeGenSchedModels::findRWForSequence(ArrayRef Seq, bool IsRead) { std::vector &RWVec = IsRead ? SchedReads : SchedWrites; for (std::vector::iterator I = RWVec.begin(), E = RWVec.end(); I != E; ++I) { - if (I->Sequence == Seq) + if (makeArrayRef(I->Sequence) == Seq) return I - RWVec.begin(); } // Index zero reserved for invalid RW. @@ -585,11 +579,11 @@ void CodeGenSchedModels::collectSchedClasses() { /// Find an SchedClass that has been inferred from a per-operand list of /// SchedWrites and SchedReads. unsigned CodeGenSchedModels::findSchedClassIdx(Record *ItinClassDef, - const IdxVec &Writes, - const IdxVec &Reads) const { + ArrayRef Writes, + ArrayRef Reads) const { for (SchedClassIter I = schedClassBegin(), E = schedClassEnd(); I != E; ++I) { - if (I->ItinClassDef == ItinClassDef - && I->Writes == Writes && I->Reads == Reads) { + if (I->ItinClassDef == ItinClassDef && makeArrayRef(I->Writes) == Writes && + makeArrayRef(I->Reads) == Reads) { return I - schedClassBegin(); } } @@ -603,20 +597,22 @@ unsigned CodeGenSchedModels::getSchedClassIdx( return InstrClassMap.lookup(Inst.TheDef); } -std::string CodeGenSchedModels::createSchedClassName( - Record *ItinClassDef, const IdxVec &OperWrites, const IdxVec &OperReads) { +std::string +CodeGenSchedModels::createSchedClassName(Record *ItinClassDef, + ArrayRef OperWrites, + ArrayRef OperReads) { std::string Name; if (ItinClassDef && ItinClassDef->getName() != "NoItinerary") Name = ItinClassDef->getName(); - for (IdxIter WI = OperWrites.begin(), WE = OperWrites.end(); WI != WE; ++WI) { + for (unsigned Idx : OperWrites) { if (!Name.empty()) Name += '_'; - Name += SchedWrites[*WI].Name; + Name += SchedWrites[Idx].Name; } - for (IdxIter RI = OperReads.begin(), RE = OperReads.end(); RI != RE; ++RI) { + for (unsigned Idx : OperReads) { Name += '_'; - Name += SchedReads[*RI].Name; + Name += SchedReads[Idx].Name; } return Name; } @@ -636,10 +632,9 @@ std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) { /// SchedWrites and SchedReads. ProcIndices contains the set of IDs of /// processors that may utilize this class. unsigned CodeGenSchedModels::addSchedClass(Record *ItinClassDef, - const IdxVec &OperWrites, - const IdxVec &OperReads, - const IdxVec &ProcIndices) -{ + ArrayRef OperWrites, + ArrayRef OperReads, + ArrayRef ProcIndices) { assert(!ProcIndices.empty() && "expect at least one ProcIdx"); unsigned Idx = findSchedClassIdx(ItinClassDef, OperWrites, OperReads); @@ -1322,10 +1317,10 @@ static void inferFromTransitions(ArrayRef LastTransitions, // Create new SchedClasses for the given ReadWrite list. If any of the // ReadWrites refers to a SchedVariant, create a new SchedClass for each variant // of the ReadWrite list, following Aliases if necessary. -void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites, - const IdxVec &OperReads, +void CodeGenSchedModels::inferFromRW(ArrayRef OperWrites, + ArrayRef OperReads, unsigned FromClassIdx, - const IdxVec &ProcIndices) { + ArrayRef ProcIndices) { DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices); dbgs() << ") "); // Create a seed transition with an empty PredTerm and the expanded sequences @@ -1335,9 +1330,9 @@ void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites, LastTransitions.back().ProcIndices.append(ProcIndices.begin(), ProcIndices.end()); - for (IdxIter I = OperWrites.begin(), E = OperWrites.end(); I != E; ++I) { + for (unsigned WriteIdx : OperWrites) { IdxVec WriteSeq; - expandRWSequence(*I, WriteSeq, /*IsRead=*/false); + expandRWSequence(WriteIdx, WriteSeq, /*IsRead=*/false); unsigned Idx = LastTransitions[0].WriteSequences.size(); LastTransitions[0].WriteSequences.resize(Idx + 1); SmallVectorImpl &Seq = LastTransitions[0].WriteSequences[Idx]; @@ -1346,9 +1341,9 @@ void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites, DEBUG(dbgs() << "("; dumpIdxVec(Seq); dbgs() << ") "); } DEBUG(dbgs() << " Reads: "); - for (IdxIter I = OperReads.begin(), E = OperReads.end(); I != E; ++I) { + for (unsigned ReadIdx : OperReads) { IdxVec ReadSeq; - expandRWSequence(*I, ReadSeq, /*IsRead=*/true); + expandRWSequence(ReadIdx, ReadSeq, /*IsRead=*/true); unsigned Idx = LastTransitions[0].ReadSequences.size(); LastTransitions[0].ReadSequences.resize(Idx + 1); SmallVectorImpl &Seq = LastTransitions[0].ReadSequences[Idx]; @@ -1552,20 +1547,16 @@ void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) { } void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead, - const IdxVec &ProcIndices) { + ArrayRef ProcIndices) { const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); if (SchedRW.TheDef) { if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) { - for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end(); - PI != PE; ++PI) { - addWriteRes(SchedRW.TheDef, *PI); - } + for (unsigned Idx : ProcIndices) + addWriteRes(SchedRW.TheDef, Idx); } else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) { - for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end(); - PI != PE; ++PI) { - addReadAdvance(SchedRW.TheDef, *PI); - } + for (unsigned Idx : ProcIndices) + addReadAdvance(SchedRW.TheDef, Idx); } } for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end(); @@ -1590,15 +1581,15 @@ void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead, } // Collect resources for a set of read/write types and processor indices. -void CodeGenSchedModels::collectRWResources(const IdxVec &Writes, - const IdxVec &Reads, - const IdxVec &ProcIndices) { +void CodeGenSchedModels::collectRWResources(ArrayRef Writes, + ArrayRef Reads, + ArrayRef ProcIndices) { - for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) - collectRWResources(*WI, /*IsRead=*/false, ProcIndices); + for (unsigned Idx : Writes) + collectRWResources(Idx, /*IsRead=*/false, ProcIndices); - for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI) - collectRWResources(*RI, /*IsRead=*/true, ProcIndices); + for (unsigned Idx : Reads) + collectRWResources(Idx, /*IsRead=*/true, ProcIndices); } diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h index e5241b9d5fd..6c34f51900c 100644 --- a/utils/TableGen/CodeGenSchedule.h +++ b/utils/TableGen/CodeGenSchedule.h @@ -72,10 +72,10 @@ struct CodeGenSchedRW { IsSequence = Def->isSubClassOf("WriteSequence"); } - CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq, + CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef Seq, const std::string &Name) - : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), - HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { + : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), + HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); } @@ -144,8 +144,9 @@ struct CodeGenSchedClass { CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {} - bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) { - return ItinClassDef == IC && Writes == W && Reads == R; + bool isKeyEqual(Record *IC, ArrayRef W, ArrayRef R) { + return ItinClassDef == IC && makeArrayRef(Writes) == W && + makeArrayRef(Reads) == R; } // Is this class generated from a variants if existing classes? Instructions @@ -363,14 +364,14 @@ public: void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead, const CodeGenProcModel &ProcModel) const; - unsigned addSchedClass(Record *ItinDef, const IdxVec &OperWrites, - const IdxVec &OperReads, const IdxVec &ProcIndices); + unsigned addSchedClass(Record *ItinDef, ArrayRef OperWrites, + ArrayRef OperReads, + ArrayRef ProcIndices); unsigned findOrInsertRW(ArrayRef Seq, bool IsRead); - unsigned findSchedClassIdx(Record *ItinClassDef, - const IdxVec &Writes, - const IdxVec &Reads) const; + unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef Writes, + ArrayRef Reads) const; Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM) const; @@ -383,14 +384,14 @@ private: void collectSchedRW(); - std::string genRWName(const IdxVec& Seq, bool IsRead); - unsigned findRWForSequence(const IdxVec &Seq, bool IsRead); + std::string genRWName(ArrayRef Seq, bool IsRead); + unsigned findRWForSequence(ArrayRef Seq, bool IsRead); void collectSchedClasses(); std::string createSchedClassName(Record *ItinClassDef, - const IdxVec &OperWrites, - const IdxVec &OperReads); + ArrayRef OperWrites, + ArrayRef OperReads); std::string createSchedClassName(const RecVec &InstDefs); void createInstRWClass(Record *InstRWDef); @@ -400,8 +401,8 @@ private: void inferSchedClasses(); - void inferFromRW(const IdxVec &OperWrites, const IdxVec &OperReads, - unsigned FromClassIdx, const IdxVec &ProcIndices); + void inferFromRW(ArrayRef OperWrites, ArrayRef OperReads, + unsigned FromClassIdx, ArrayRef ProcIndices); void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx); void inferFromInstRWs(unsigned SCIdx); @@ -413,10 +414,10 @@ private: void collectItinProcResources(Record *ItinClassDef); void collectRWResources(unsigned RWIdx, bool IsRead, - const IdxVec &ProcIndices); + ArrayRef ProcIndices); - void collectRWResources(const IdxVec &Writes, const IdxVec &Reads, - const IdxVec &ProcIndices); + void collectRWResources(ArrayRef Writes, ArrayRef Reads, + ArrayRef ProcIndices); void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM); -- 2.34.1