From 10e044c04269c8fd32e9d3eac12f8ce114a7df58 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Tue, 6 Oct 2015 15:17:25 +0000 Subject: [PATCH] [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backend Summary: This fixes 7 tests during fast LLVM test-suite run: * MultiSource/Benchmarks/McCat/18-imp/imp * MultiSource/Applications/oggenc/oggenc * MultiSource/Benchmarks/MallocBench/gs/gs * MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan * MultiSource/Benchmarks/VersaBench/beamformer/beamformer * MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame * MultiSource/Benchmarks/Bullet/bullet Error message was in the form of: fatal error: error in backend: Cannot select: 0x95c3288: f32 = fsqrt 0x95c0190 [ORD=9] [ID=18] 0x95c0190: f32 = fadd 0x95bef30, 0x95c4d00 [ORD=8] [ID=17] 0x95bef30: f32 = fmul 0x95c4988, 0x95c4988 [ORD=5] [ID=16] ... There was problem with selecting sqrt instruction in LLVM backend. To fix the issue changes are made in TableGen definition for sqrt instruction in MipsInstrFPU.td and new test file sqrt.ll is added to LLVM regression tests. Patch by Zlatko Buljan Reviewers: zoran.jovanovic, hvarga, dsanders Subscribers: llvm-commits, petarj Differential Revision: http://reviews.llvm.org/D13235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249416 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrFPU.td | 7 ++----- test/CodeGen/Mips/llvm-ir/sqrt.ll | 13 +++++++++++++ 2 files changed, 15 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/Mips/llvm-ir/sqrt.ll diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 9b9d5f6cc2e..d1a72494433 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -353,11 +353,8 @@ def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; -let AdditionalPredicates = [NotInMicroMips] in { -def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, - ABSS_FM<0x4, 16>, ISA_MIPS2; -} - +def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, + II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; // The odd-numbered registers are only referenced when doing loads, diff --git a/test/CodeGen/Mips/llvm-ir/sqrt.ll b/test/CodeGen/Mips/llvm-ir/sqrt.ll new file mode 100644 index 00000000000..1a8892de0ee --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sqrt.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s + +define float @sqrt_fn(float %value) #0 { +entry: + %sqrtf = tail call float @sqrtf(float %value) #0 + ret float %sqrtf +} + +declare float @sqrtf(float) + +; CHECK: sqrt.s $f0, $f12 -- 2.34.1