From 1193299d11adbb031383bebece73abb6b431f865 Mon Sep 17 00:00:00 2001 From: chenxing Date: Sat, 20 Jul 2013 14:41:50 +0800 Subject: [PATCH] rk2928: pm.c refactoring as rk30 --- arch/arm/mach-rk2928/pm.c | 581 ++++++++++++++++++++++++++------------ 1 file changed, 394 insertions(+), 187 deletions(-) diff --git a/arch/arm/mach-rk2928/pm.c b/arch/arm/mach-rk2928/pm.c index 470bdfa19502..307a8f71d568 100644 --- a/arch/arm/mach-rk2928/pm.c +++ b/arch/arm/mach-rk2928/pm.c @@ -35,25 +35,29 @@ cru_writel(((~(val) | (_save)) & (w_msk)) | ((w_msk) << 16), cons); \ } while (0) +#define RK_SOC_PM_CTR_FUN(ctr,fun) \ + if(!(rk_soc_pm_ctr_bits_check((1<>13);// 16.7s max + g_crc1 = calc_crc32((u32) _stext, (size_t)(_etext - _stext)); + nMHz = (random32() >> 13); // 16.7s max ddr_suspend(); sram_udelay(nMHz); ddr_resume(); sram_printhex(nMHz); sram_printch(' '); sram_printhex(n++); - g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext)); + g_crc2 = calc_crc32((u32) _stext, (size_t)(_etext - _stext)); + if (g_crc1 != g_crc2) { sram_printch(' '); sram_printch('f'); @@ -140,6 +266,7 @@ static void ddr_testmode(void) sram_printch('i'); sram_printch('l'); } + // ddr_print("check image crc32 fail!, count:%d\n", n++); // sram_printascii("self refresh fail\n"); //else @@ -149,11 +276,9 @@ static void ddr_testmode(void) } else if (ddr_debug == 3) { extern int memtester(void); memtester(); - } - else - { - ddr_change_freq(ddr_debug); - ddr_debug=0; + } else { + ddr_change_freq(ddr_debug); + ddr_debug = 0; } } #else @@ -164,28 +289,32 @@ static noinline void rk2928_pm_dump_irq(void) { u32 irq_gpio = (readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + (IRQ_GPIO0 / 32) * 4) >> (IRQ_GPIO0 % 32)) & 0xF; printk("wakeup irq: %08x %08x %08x\n", - readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4), - readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8), - readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12)); + readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 4), + readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 8), + readl_relaxed(RK2928_GICD_BASE + GIC_DIST_PENDING_SET + 12)); + if (irq_gpio & 1) printk("wakeup gpio0: %08x\n", readl_relaxed(RK2928_GPIO0_BASE + GPIO_INT_STATUS)); + if (irq_gpio & 2) printk("wakeup gpio1: %08x\n", readl_relaxed(RK2928_GPIO1_BASE + GPIO_INT_STATUS)); + if (irq_gpio & 4) printk("wakeup gpio2: %08x\n", readl_relaxed(RK2928_GPIO2_BASE + GPIO_INT_STATUS)); + if (irq_gpio & 8) printk("wakeup gpio3: %08x\n", readl_relaxed(RK2928_GPIO3_BASE + GPIO_INT_STATUS)); } #define DUMP_GPIO_INTEN(ID) \ -do { \ - u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \ - if (en) { \ - sram_printascii("GPIO" #ID "_INTEN: "); \ - sram_printhex(en); \ - sram_printch('\n'); \ - } \ -} while (0) + do { \ + u32 en = readl_relaxed(RK2928_GPIO##ID##_BASE + GPIO_INTEN); \ + if (en) { \ + sram_printascii("GPIO" #ID "_INTEN: "); \ + sram_printhex(en); \ + sram_printch('\n'); \ + } \ + } while (0) static noinline void rk2928_pm_dump_inten(void) { @@ -197,38 +326,39 @@ static noinline void rk2928_pm_dump_inten(void) static void pm_pll_wait_lock(int pll_idx) { - u32 pll_state[4] = {1, 0, 2, 3}; - u32 bit = 0x10u << pll_state[pll_idx]; int delay = 24000000; + while (delay > 0) { if ((cru_readl(PLL_CONS(pll_idx, 1)) & (0x1 << PLL_LOCK_SHIFT))) { break; } + delay--; } + if (delay == 0) { sram_printch('p'); sram_printch('l'); sram_printch('l'); sram_printhex(pll_idx); sram_printch('\n'); - while(1); + + while (1); } } #define power_on_pll(id) \ cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\ - pm_pll_wait_lock((id)) +pm_pll_wait_lock((id)) static int pm_pll_pwr_up(u8 pll_id) { - u32 pllcon0,pllcon1,pllcon2; //enter slowmode cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON); - cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01), PLL_CONS(pll_id, 1)); - + cru_writel(CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01), PLL_CONS(pll_id, 1)); + sram_udelay(100); - + pm_pll_wait_lock(pll_id); //return form slow //cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON); @@ -248,8 +378,9 @@ static noinline void interface_ctr_reg_pread(void) outer_flush_all(); local_flush_tlb_all(); - for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)SRAM_DATA_END; addr += PAGE_SIZE) + for (addr = (u32) SRAM_CODE_OFFSET; addr < (u32) SRAM_DATA_END; addr += PAGE_SIZE) readl_relaxed(addr); + readl_relaxed(RK2928_GRF_BASE); readl_relaxed(RK2928_DDR_PCTL_BASE); readl_relaxed(RK2928_DDR_PHY_BASE); @@ -257,11 +388,11 @@ static noinline void interface_ctr_reg_pread(void) readl_relaxed(RK2928_GPIO1_BASE); readl_relaxed(RK2928_GPIO2_BASE); readl_relaxed(RK2928_GPIO3_BASE); - #if defined (CONFIG_MACH_RK2928_SDK) +#if defined (CONFIG_MACH_RK2928_SDK) readl_relaxed(RK2928_RKI2C1_BASE); - #else +#else readl_relaxed(RK2928_RKI2C0_BASE); - #endif +#endif } __weak void board_gpio_suspend(void) {} @@ -277,80 +408,126 @@ __weak void rk30_pwm_resume_voltage_set(void) {} __weak void __sramfunc rk30_pwm_logic_suspend_voltage(void) {} __weak void __sramfunc rk30_pwm_logic_resume_voltage(void) {} -static void __sramfunc rk2928_sram_suspend(void) +#define CLK_GATE0_W_MSK (0xffff) +#define CLK_GATE1_W_MSK (0xffff) //defult:(0xffff); ignore usb:(0xff9f) G1_[6:5] +#define CLK_GATE2_W_MSK (0xffff) +#define CLK_GATE3_W_MSK (0xffff) //defult:(0xff9f); ignore use:(0xff9f) G3_[6] +#define CLK_GATE4_W_MSK (0xffff) +#define CLK_GATE5_W_MSK (0xffff) //defult:(0xffff); ignore usb:(0xdfff) G5_[13] +#define CLK_GATE6_W_MSK (0xffff) +#define CLK_GATE7_W_MSK (0xffff) //defult:(0xffff); ignore usb:(0xffe7) G7_[4:3] +#define CLK_GATE8_W_MSK (0xffff) +#define CLK_GATE9_W_MSK (0xffff) +static u32 __sramdata clkgt_regs_sram[CRU_CLKGATES_CON_CNT]; +static u32 __sramdata grf_uoc1_con; +static void __sramfunc rk_pm_soc_sram_volt_suspend(void) { - u32 cru_clksel0_con; - u32 clkgt_regs[CRU_CLKGATES_CON_CNT]; - int i; - u32 grf_uoc1_con; - - sram_printch('5'); - ddr_suspend(); - sram_printch('6'); rk30_suspend_voltage_set(1000000); rk30_pwm_logic_suspend_voltage(); board_pmu_suspend(); - sram_printch('7'); +} + +static void __sramfunc rk_pm_soc_sram_clk_gating(void) +{ + int i; #ifdef CONFIG_ARCH_RK2928 - grf_uoc1_con = grf_readl(GRF_UOC1_CON4); - grf_writel(0x30000000,GRF_UOC1_CON4); + grf_uoc1_con = grf_readl(GRF_UOC1_CON4); + grf_writel(0x30000000, GRF_UOC1_CON4); #endif + for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) { - clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i)); + clkgt_regs_sram[i] = cru_readl(CRU_CLKGATES_CON(i)); } + gate_save_soc_clk(0 - | (1 << CLK_GATE_CORE_PERIPH) - | (1 << CLK_GATE_DDRPHY_SRC) - | (1 << CLK_GATE_ACLK_CPU) - | (1 << CLK_GATE_HCLK_CPU) - | (1 << CLK_GATE_PCLK_CPU) - | (1 << CLK_GATE_ACLK_CORE) - , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff); - if (((clkgt_regs[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) != 0xf) { + | (1 << CLK_GATE_CORE_PERIPH) + | (1 << CLK_GATE_DDRPHY_SRC) + | (1 << CLK_GATE_ACLK_CPU) + | (1 << CLK_GATE_HCLK_CPU) + | (1 << CLK_GATE_PCLK_CPU) + | (1 << CLK_GATE_ACLK_CORE) + , clkgt_regs_sram[0], CRU_CLKGATES_CON(0), CLK_GATE0_W_MSK); + + if (((clkgt_regs_sram[8] >> (CLK_GATE_PCLK_GPIO0 % 16)) & 0xf) != 0xf) { gate_save_soc_clk(0 - | (1 << CLK_GATE_PERIPH_SRC % 16) - | (1 << CLK_GATE_PCLK_PERIPH % 16) - , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff); + | (1 << CLK_GATE_PERIPH_SRC % 16) + | (1 << CLK_GATE_PCLK_PERIPH % 16) + , clkgt_regs_sram[2], CRU_CLKGATES_CON(2), CLK_GATE2_W_MSK); } else { - gate_save_soc_clk(0, clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff); + gate_save_soc_clk(0, clkgt_regs_sram[2], CRU_CLKGATES_CON(2), CLK_GATE2_W_MSK); } + gate_save_soc_clk(0 - | (1 << CLK_GATE_ACLK_STRC_SYS % 16) - | (1 << CLK_GATE_ACLK_INTMEM % 16) - , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff); + | (1 << CLK_GATE_ACLK_STRC_SYS % 16) + | (1 << CLK_GATE_ACLK_INTMEM % 16) + , clkgt_regs_sram[4], CRU_CLKGATES_CON(4), CLK_GATE4_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_PCLK_GRF % 16) - | (1 << CLK_GATE_PCLK_DDRUPCTL % 16) - , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff); - gate_save_soc_clk(0, clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff); + | (1 << CLK_GATE_PCLK_GRF % 16) + | (1 << CLK_GATE_PCLK_DDRUPCTL % 16) + , clkgt_regs_sram[5], CRU_CLKGATES_CON(5), CLK_GATE5_W_MSK); + gate_save_soc_clk(0, clkgt_regs_sram[7], CRU_CLKGATES_CON(7), CLK_GATE7_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_CLK_L2C % 16) - , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff); + | (1 << CLK_GATE_CLK_L2C % 16) + , clkgt_regs_sram[9], CRU_CLKGATES_CON(9), CLK_GATE9_W_MSK); +} -// board_pmu_suspend(); - cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0)); - cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0)); +static u32 __sramdata sram_cru_clksel0_con; +static void __sramfunc rk_pm_soc_sram_sys_clk_suspend(void) +{ + sram_cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0)); + cru_writel(CLK_CORE_DIV(32), CRU_CLKSELS_CON(0)); - dsb(); - wfi(); +} +static void __sramfunc rk_pm_soc_sram_sys_clk_resume(void) +{ + + cru_writel((0x1f << 16) | sram_cru_clksel0_con, CRU_CLKSELS_CON(0)); + //cru_writel((A9_CORE_DIV_MASK << (A9_CORE_DIV_SHIFT + 16)) | sram_cru_clksel0_con, CRU_CLKSELS_CON(0)); - cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0)); -// board_pmu_resume(); +} +static void __sramfunc rk_pm_soc_sram_clk_ungating(void) +{ + int i; for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) { - cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i)); + cru_writel(clkgt_regs_sram[i] | 0xffff0000, CRU_CLKGATES_CON(i)); } #ifdef CONFIG_ARCH_RK2928 - grf_writel(0x30000000|grf_uoc1_con,GRF_UOC1_CON4); + grf_writel(0x30000000 | grf_uoc1_con, GRF_UOC1_CON4); #endif - sram_printch('7'); +} + +static void __sramfunc rk_pm_soc_sram_volt_resume(void) +{ board_pmu_resume(); rk30_pwm_logic_resume_voltage(); rk30_suspend_voltage_resume(1100000); +} +static void __sramfunc rk2928_sram_suspend(void) +{ + sram_printch('5'); + RK_SOC_PM_CTR_FUN(NO_DDR, ddr_suspend); sram_printch('6'); - ddr_resume(); + RK_SOC_PM_CTR_FUN(NO_VOLT, rk_pm_soc_sram_volt_suspend); + sram_printch('7'); + RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_sram_clk_gating); + RK_SOC_PM_CTR_FUN(NO_SYS_CLK, rk_pm_soc_sram_sys_clk_suspend); + + //RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_suspend); + if (!rk_soc_pm_ctr_bits_check(RK_SUSPEND_NO_SRAM_WFI_BITS)) { + dsb(); + wfi(); + } + + //RK_SOC_PM_CTR_FUN(NO_PMIC,board_pmu_resume); + RK_SOC_PM_CTR_FUN(NO_SYS_CLK, rk_pm_soc_sram_sys_clk_resume); + RK_SOC_PM_CTR_FUN(NO_CLK_GATING, rk_pm_soc_sram_clk_ungating); + sram_printch('7'); + RK_SOC_PM_CTR_FUN(NO_VOLT, rk_pm_soc_sram_volt_resume); + sram_printch('6'); + RK_SOC_PM_CTR_FUN(NO_DDR, ddr_resume); sram_printch('5'); } static void noinline rk2928_suspend(void) @@ -359,123 +536,101 @@ static void noinline rk2928_suspend(void) rk2928_sram_suspend(); DDR_RESTORE_SP(save_sp); } - -static int rk2928_pm_enter(suspend_state_t state) +static u32 clk_sel0, clk_sel1, clk_sel10; +static u32 cru_mode_con; +static u32 apll_con1, cpll_con1, gpll_con1; +static u32 clkgt_regs_first[CRU_CLKGATES_CON_CNT]; +static void rk_pm_soc_clk_gating_first(void) { - u32 i; - u32 clkgt_regs[CRU_CLKGATES_CON_CNT]; - u32 clk_sel0, clk_sel1, clk_sel10; - u32 cru_mode_con; - u32 apll_con1,cpll_con1,gpll_con1; - // dump GPIO INTEN for debug - rk2928_pm_dump_inten(); - - sram_printch('0'); - -#ifdef CONFIG_DDR_TEST - // memory tester - if (ddr_debug != 0) - ddr_testmode(); -#endif - - sram_printch('1'); - local_fiq_disable(); + int i; for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) { - clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i)); + clkgt_regs_first[i] = cru_readl(CRU_CLKGATES_CON(i)); } gate_save_soc_clk(0 - | (1 << CLK_GATE_CORE_PERIPH) - | (1 << CLK_GATE_CPU_GPLL) - | (1 << CLK_GATE_DDRPHY_SRC) - | (1 << CLK_GATE_ACLK_CPU) - | (1 << CLK_GATE_HCLK_CPU) - | (1 << CLK_GATE_PCLK_CPU) - | (1 << CLK_GATE_ACLK_CORE) - , clkgt_regs[0], CRU_CLKGATES_CON(0), 0xffff); - gate_save_soc_clk(0, clkgt_regs[1], CRU_CLKGATES_CON(1), 0xffff); + | (1 << CLK_GATE_CORE_PERIPH) + | (1 << CLK_GATE_CPU_GPLL) + | (1 << CLK_GATE_DDRPHY_SRC) + | (1 << CLK_GATE_ACLK_CPU) + | (1 << CLK_GATE_HCLK_CPU) + | (1 << CLK_GATE_PCLK_CPU) + | (1 << CLK_GATE_ACLK_CORE) + , clkgt_regs_first[0], CRU_CLKGATES_CON(0), CLK_GATE0_W_MSK); + gate_save_soc_clk(0, clkgt_regs_first[1], CRU_CLKGATES_CON(1), CLK_GATE1_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_PERIPH_SRC % 16) - | (1 << CLK_GATE_PCLK_PERIPH % 16) - | (1 << CLK_GATE_ACLK_PERIPH % 16) - , clkgt_regs[2], CRU_CLKGATES_CON(2), 0xffff); - gate_save_soc_clk(0, clkgt_regs[3], CRU_CLKGATES_CON(3), 0xffff); + | (1 << CLK_GATE_PERIPH_SRC % 16) + | (1 << CLK_GATE_PCLK_PERIPH % 16) + | (1 << CLK_GATE_ACLK_PERIPH % 16) + , clkgt_regs_first[2], CRU_CLKGATES_CON(2), CLK_GATE2_W_MSK); + gate_save_soc_clk(0, clkgt_regs_first[3], CRU_CLKGATES_CON(3), CLK_GATE3_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16) - | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16) - | (1 << CLK_GATE_ACLK_CPU_PERI % 16) - | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16) - | (1 << CLK_GATE_ACLK_STRC_SYS % 16) - | (1 << CLK_GATE_ACLK_INTMEM % 16) - , clkgt_regs[4], CRU_CLKGATES_CON(4), 0xffff); + | (1 << CLK_GATE_HCLK_PERI_AXI_MATRIX % 16) + | (1 << CLK_GATE_PCLK_PERI_AXI_MATRIX % 16) + | (1 << CLK_GATE_ACLK_CPU_PERI % 16) + | (1 << CLK_GATE_ACLK_PERI_AXI_MATRIX % 16) + | (1 << CLK_GATE_ACLK_STRC_SYS % 16) + | (1 << CLK_GATE_ACLK_INTMEM % 16) + , clkgt_regs_first[4], CRU_CLKGATES_CON(4), CLK_GATE4_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_PCLK_GRF % 16) - | (1 << CLK_GATE_PCLK_DDRUPCTL % 16) - , clkgt_regs[5], CRU_CLKGATES_CON(5), 0xffff); - gate_save_soc_clk(0, clkgt_regs[6], CRU_CLKGATES_CON(6), 0xffff); + | (1 << CLK_GATE_PCLK_GRF % 16) + | (1 << CLK_GATE_PCLK_DDRUPCTL % 16) + , clkgt_regs_first[5], CRU_CLKGATES_CON(5), CLK_GATE5_W_MSK); + gate_save_soc_clk(0, clkgt_regs_first[6], CRU_CLKGATES_CON(6), CLK_GATE6_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_PCLK_PWM01 % 16) - , clkgt_regs[7], CRU_CLKGATES_CON(7), 0xffff); + | (1 << CLK_GATE_PCLK_PWM01 % 16) + , clkgt_regs_first[7], CRU_CLKGATES_CON(7), CLK_GATE7_W_MSK); gate_save_soc_clk(0 - | (1 << CLK_GATE_PCLK_GPIO0 % 16) - | (1 << CLK_GATE_PCLK_GPIO1 % 16) - | (1 << CLK_GATE_PCLK_GPIO2 % 16) - | (1 << CLK_GATE_PCLK_GPIO3 % 16) - , clkgt_regs[8], CRU_CLKGATES_CON(8), 0xffff); - cru_writel( ((1 << CLK_GATE_PCLK_GPIO0 % 16)<<16), CRU_CLKGATES_CON(8)); + | (1 << CLK_GATE_PCLK_GPIO0 % 16) + | (1 << CLK_GATE_PCLK_GPIO1 % 16) + | (1 << CLK_GATE_PCLK_GPIO2 % 16) + | (1 << CLK_GATE_PCLK_GPIO3 % 16) + , clkgt_regs_first[8], CRU_CLKGATES_CON(8), CLK_GATE8_W_MSK); + cru_writel(((1 << CLK_GATE_PCLK_GPIO0 % 16) << 16), CRU_CLKGATES_CON(8)); gate_save_soc_clk(0 - | (1 << CLK_GATE_CLK_L2C % 16) - | (1 << CLK_GATE_HCLK_PERI_ARBI % 16) - | (1 << CLK_GATE_ACLK_PERI_NIU % 16) - , clkgt_regs[9], CRU_CLKGATES_CON(9), 0xffff); + | (1 << CLK_GATE_CLK_L2C % 16) + | (1 << CLK_GATE_HCLK_PERI_ARBI % 16) + | (1 << CLK_GATE_ACLK_PERI_NIU % 16) + , clkgt_regs_first[9], CRU_CLKGATES_CON(9), CLK_GATE9_W_MSK); - sram_printch('2'); +} +static void rk_pm_soc_pll_suspend(void) +{ cru_mode_con = cru_readl(CRU_MODE_CON); //apll clk_sel0 = cru_readl(CRU_CLKSELS_CON(0)); clk_sel1 = cru_readl(CRU_CLKSELS_CON(1)); apll_con1 = cru_readl(PLL_CONS(APLL_ID, 1)); - + cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON); cru_writel(CLK_CORE_DIV(1) | ACLK_CPU_DIV(1) | CPU_SEL_PLL(SEL_APLL), CRU_CLKSELS_CON(0)); cru_writel(CLK_CORE_PERI_DIV(1) | ACLK_CORE_DIV(1) | HCLK_CPU_DIV(1) | PCLK_CPU_DIV(1), CRU_CLKSELS_CON(1)); - //cru_writel((0x01 <<(PLL_PWR_DN_SHIFT + 16))|(1<