From 11a106d8981ff1cab4510c634761eafa0b96714c Mon Sep 17 00:00:00 2001 From: xxx Date: Tue, 7 May 2013 17:17:31 +0800 Subject: [PATCH] board-rk3168-tb.c use default pll rate --- arch/arm/mach-rk30/board-rk3168-tb.c | 3 +-- arch/arm/mach-rk3188/clock_data.c | 1 - arch/arm/mach-rk3188/include/mach/board.h | 9 ++------- 3 files changed, 3 insertions(+), 10 deletions(-) mode change 100644 => 100755 arch/arm/mach-rk30/board-rk3168-tb.c diff --git a/arch/arm/mach-rk30/board-rk3168-tb.c b/arch/arm/mach-rk30/board-rk3168-tb.c old mode 100644 new mode 100755 index e91118552272..ea2cebf2310d --- a/arch/arm/mach-rk30/board-rk3168-tb.c +++ b/arch/arm/mach-rk30/board-rk3168-tb.c @@ -2579,8 +2579,7 @@ static struct cpufreq_frequency_table dvfs_ddr_table[] = { void __init board_clock_init(void) { - rk30_clock_data_init(periph_pll_384mhz, codec_pll_594mhz, RK30_CLOCKS_DEFAULT_FLAGS); - //rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS); + rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS); //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table); dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table); dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table); diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c index 99c1e1d939e2..689c8a10fe19 100755 --- a/arch/arm/mach-rk3188/clock_data.c +++ b/arch/arm/mach-rk3188/clock_data.c @@ -3430,7 +3430,6 @@ void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk) clk_set_rate_nolock(&clk_uart1_div,rate); clk_set_rate_nolock(&clk_uart2_div,rate); clk_set_rate_nolock(&clk_uart3_div,rate); - clk_set_rate_nolock(&clk_uart1,rate); } static void inline clock_set_div(struct clk *clk,u32 div) diff --git a/arch/arm/mach-rk3188/include/mach/board.h b/arch/arm/mach-rk3188/include/mach/board.h index 2ebb501ff296..2dd3dcef90a5 100755 --- a/arch/arm/mach-rk3188/include/mach/board.h +++ b/arch/arm/mach-rk3188/include/mach/board.h @@ -75,13 +75,8 @@ enum _codec_pll { #define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/) -#if (RK30_CLOCKS_DEFAULT_FLAGS&CLK_FLG_UART_1_3M) -#define codec_pll_default codec_pll_768mhz -#else -#define codec_pll_default codec_pll_798mhz -#endif -#define periph_pll_default periph_pll_594mhz - +#define codec_pll_default codec_pll_594mhz +#define periph_pll_default periph_pll_384mhz #endif -- 2.34.1