From 124c86ee4a9a4d63e488abcba931175b6fd9f42b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 9 Mar 2014 18:03:14 +0000 Subject: [PATCH] [C++11] Add 'override' keyword to virtual methods that override their base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203418 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/AsmParser/X86AsmParser.cpp | 12 +++--- lib/Target/X86/AsmParser/X86Operand.h | 26 ++++++------- lib/Target/X86/Disassembler/X86Disassembler.h | 8 ++-- .../X86/InstPrinter/X86IntelInstPrinter.h | 6 +-- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 39 +++++++++---------- .../X86/MCTargetDesc/X86ELFObjectWriter.cpp | 6 +-- .../X86/MCTargetDesc/X86ELFRelocationInfo.cpp | 2 +- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h | 18 ++++----- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 2 +- .../MCTargetDesc/X86MachORelocationInfo.cpp | 2 +- .../X86/MCTargetDesc/X86MachObjectWriter.cpp | 2 +- utils/TableGen/AsmMatcherEmitter.cpp | 4 +- 12 files changed, 62 insertions(+), 65 deletions(-) diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 76c59cdb400..5f5f66b0972 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -653,7 +653,7 @@ private: bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl &Operands, MCStreamer &Out, unsigned &ErrorInfo, - bool MatchingInlineAsm); + bool MatchingInlineAsm) override; /// doSrcDstMatch - Returns true if operands are matching in their /// word size (%si and %di, %esi and %edi, etc.). Order depends on @@ -707,13 +707,13 @@ public: // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; - virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, - SMLoc NameLoc, - SmallVectorImpl &Operands); + bool + ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, + SmallVectorImpl &Operands) override; - virtual bool ParseDirective(AsmToken DirectiveID); + bool ParseDirective(AsmToken DirectiveID) override; }; } // end anonymous namespace diff --git a/lib/Target/X86/AsmParser/X86Operand.h b/lib/Target/X86/AsmParser/X86Operand.h index 54d7b7785cc..45fe2a9d0c2 100644 --- a/lib/Target/X86/AsmParser/X86Operand.h +++ b/lib/Target/X86/AsmParser/X86Operand.h @@ -64,20 +64,20 @@ struct X86Operand : public MCParsedAsmOperand { X86Operand(KindTy K, SMLoc Start, SMLoc End) : Kind(K), StartLoc(Start), EndLoc(End) {} - StringRef getSymName() { return SymName; } - void *getOpDecl() { return OpDecl; } + StringRef getSymName() override { return SymName; } + void *getOpDecl() override { return OpDecl; } /// getStartLoc - Get the location of the first token of this operand. - SMLoc getStartLoc() const { return StartLoc; } + SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. - SMLoc getEndLoc() const { return EndLoc; } + SMLoc getEndLoc() const override { return EndLoc; } /// getLocRange - Get the range between the first and last token of this /// operand. SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } /// getOffsetOfLoc - Get the location of the offset operator. - SMLoc getOffsetOfLoc() const { return OffsetOfLoc; } + SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; } - virtual void print(raw_ostream &OS) const {} + void print(raw_ostream &OS) const override {} StringRef getToken() const { assert(Kind == Token && "Invalid access!"); @@ -89,7 +89,7 @@ struct X86Operand : public MCParsedAsmOperand { Tok.Length = Value.size(); } - unsigned getReg() const { + unsigned getReg() const override { assert(Kind == Register && "Invalid access!"); return Reg.RegNo; } @@ -120,9 +120,9 @@ struct X86Operand : public MCParsedAsmOperand { return Mem.Scale; } - bool isToken() const {return Kind == Token; } + bool isToken() const override {return Kind == Token; } - bool isImm() const { return Kind == Immediate; } + bool isImm() const override { return Kind == Immediate; } bool isImmSExti16i8() const { if (!isImm()) @@ -195,15 +195,15 @@ struct X86Operand : public MCParsedAsmOperand { return isImmSExti64i32Value(CE->getValue()); } - bool isOffsetOf() const { + bool isOffsetOf() const override { return OffsetOfLoc.getPointer(); } - bool needAddressOf() const { + bool needAddressOf() const override { return AddressOf; } - bool isMem() const { return Kind == Memory; } + bool isMem() const override { return Kind == Memory; } bool isMem8() const { return Kind == Memory && (!Mem.Size || Mem.Size == 8); } @@ -315,7 +315,7 @@ struct X86Operand : public MCParsedAsmOperand { !getMemIndexReg() && getMemScale() == 1 && (!Mem.Size || Mem.Size == 64); } - bool isReg() const { return Kind == Register; } + bool isReg() const override { return Kind == Register; } bool isGR32orGR64() const { return Kind == Register && diff --git a/lib/Target/X86/Disassembler/X86Disassembler.h b/lib/Target/X86/Disassembler/X86Disassembler.h index b2959c06566..4e6e2971aac 100644 --- a/lib/Target/X86/Disassembler/X86Disassembler.h +++ b/lib/Target/X86/Disassembler/X86Disassembler.h @@ -111,12 +111,10 @@ private: public: /// getInstruction - See MCDisassembler. - DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, raw_ostream &vStream, - raw_ostream &cStream) const; + raw_ostream &cStream) const override; private: DisassemblerMode fMode; diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h index 47b65b2b365..43490892adf 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h @@ -27,9 +27,9 @@ public: const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; - virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot); - + void printRegName(raw_ostream &OS, unsigned RegNo) const override; + void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override; + // Autogenerated by tblgen. void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); diff --git a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index 440bbf0d4f1..8830e643fd9 100644 --- a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -79,11 +79,11 @@ public: CPU != "c3" && CPU != "c3-2"; } - unsigned getNumFixupKinds() const { + unsigned getNumFixupKinds() const override { return X86::NumTargetFixupKinds; } - const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }, { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel}, @@ -100,7 +100,7 @@ public: } void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const { + uint64_t Value) const override { unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); assert(Fixup.getOffset() + Size <= DataSize && @@ -117,16 +117,15 @@ public: Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); } - bool mayNeedRelaxation(const MCInst &Inst) const; + bool mayNeedRelaxation(const MCInst &Inst) const override; - bool fixupNeedsRelaxation(const MCFixup &Fixup, - uint64_t Value, + bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, - const MCAsmLayout &Layout) const; + const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, MCInst &Res) const; + void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; - bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; }; } // end anonymous namespace @@ -355,7 +354,7 @@ public: ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) : ELFX86AsmBackend(T, OSABI, CPU) {} - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); } }; @@ -365,7 +364,7 @@ public: ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) : ELFX86AsmBackend(T, OSABI, CPU) {} - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); } }; @@ -379,7 +378,7 @@ public: , Is64Bit(is64Bit) { } - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createX86WinCOFFObjectWriter(OS, Is64Bit); } }; @@ -718,15 +717,15 @@ public: StringRef CPU, bool SupportsCU) : DarwinX86AsmBackend(T, MRI, CPU, false), SupportsCU(SupportsCU) {} - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPU_TYPE_I386, MachO::CPU_SUBTYPE_I386_ALL); } /// \brief Generate the compact unwind encoding for the CFI instructions. - virtual uint32_t - generateCompactUnwindEncoding(ArrayRef Instrs) const { + uint32_t generateCompactUnwindEncoding( + ArrayRef Instrs) const override { return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0; } }; @@ -743,12 +742,12 @@ public: HasReliableSymbolDifference = true; } - MCObjectWriter *createObjectWriter(raw_ostream &OS) const { + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/true, MachO::CPU_TYPE_X86_64, Subtype); } - virtual bool doesSectionRequireSymbols(const MCSection &Section) const { + bool doesSectionRequireSymbols(const MCSection &Section) const override { // Temporary labels in the string literals sections require symbols. The // issue is that the x86_64 relocation format does not allow symbol + // offset, and so the linker does not have enough information to resolve the @@ -761,7 +760,7 @@ public: return SMO.getType() == MachO::S_CSTRING_LITERALS; } - virtual bool isSectionAtomizable(const MCSection &Section) const { + bool isSectionAtomizable(const MCSection &Section) const override { const MCSectionMachO &SMO = static_cast(Section); // Fixed sized data sections are uniqued, they cannot be diced into atoms. switch (SMO.getType()) { @@ -782,8 +781,8 @@ public: } /// \brief Generate the compact unwind encoding for the CFI instructions. - virtual uint32_t - generateCompactUnwindEncoding(ArrayRef Instrs) const { + uint32_t generateCompactUnwindEncoding( + ArrayRef Instrs) const override { return SupportsCU ? generateCompactUnwindEncodingImpl(Instrs) : 0; } }; diff --git a/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp b/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp index 64344e45218..7118a6f6dc5 100644 --- a/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86ELFObjectWriter.cpp @@ -24,9 +24,9 @@ namespace { virtual ~X86ELFObjectWriter(); protected: - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const; + unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const override; }; } diff --git a/lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp b/lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp index f00a8befba9..4fa519c9ba1 100644 --- a/lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp +++ b/lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp @@ -25,7 +25,7 @@ class X86_64ELFRelocationInfo : public MCRelocationInfo { public: X86_64ELFRelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {} - const MCExpr *createExprForRelocation(RelocationRef Rel) { + const MCExpr *createExprForRelocation(RelocationRef Rel) override { uint64_t RelType; Rel.getType(RelType); symbol_iterator SymI = Rel.getSymbol(); diff --git a/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h b/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h index 80979dda677..a7509b03809 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h +++ b/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h @@ -23,34 +23,34 @@ namespace llvm { class Triple; class X86MCAsmInfoDarwin : public MCAsmInfoDarwin { - virtual void anchor(); + void anchor() override; public: explicit X86MCAsmInfoDarwin(const Triple &Triple); }; struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin { explicit X86_64MCAsmInfoDarwin(const Triple &Triple); - virtual const MCExpr * - getExprForPersonalitySymbol(const MCSymbol *Sym, - unsigned Encoding, - MCStreamer &Streamer) const; + const MCExpr * + getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, + MCStreamer &Streamer) const override; }; class X86ELFMCAsmInfo : public MCAsmInfoELF { - virtual void anchor(); + void anchor() override; public: explicit X86ELFMCAsmInfo(const Triple &Triple); - virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) const; + const MCSection * + getNonexecutableStackSection(MCContext &Ctx) const override; }; class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { - virtual void anchor(); + void anchor() override; public: explicit X86MCAsmInfoMicrosoft(const Triple &Triple); }; class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF { - virtual void anchor(); + void anchor() override; public: explicit X86MCAsmInfoGNUCOFF(const Triple &Triple); }; diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index b4e8b7a67f4..e6fb0377f00 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -150,7 +150,7 @@ public: void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const; + const MCSubtargetInfo &STI) const override; void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, diff --git a/lib/Target/X86/MCTargetDesc/X86MachORelocationInfo.cpp b/lib/Target/X86/MCTargetDesc/X86MachORelocationInfo.cpp index 024bdb75b4e..f2023e3b525 100644 --- a/lib/Target/X86/MCTargetDesc/X86MachORelocationInfo.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MachORelocationInfo.cpp @@ -24,7 +24,7 @@ class X86_64MachORelocationInfo : public MCRelocationInfo { public: X86_64MachORelocationInfo(MCContext &Ctx) : MCRelocationInfo(Ctx) {} - const MCExpr *createExprForRelocation(RelocationRef Rel) { + const MCExpr *createExprForRelocation(RelocationRef Rel) override { const MachOObjectFile *Obj = cast(Rel.getObjectFile()); uint64_t RelType; Rel.getType(RelType); diff --git a/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp b/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp index a827d22bd5a..1a35ced166b 100644 --- a/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MachObjectWriter.cpp @@ -63,7 +63,7 @@ public: void RecordRelocation(MachObjectWriter *Writer, const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, - MCValue Target, uint64_t &FixedValue) { + MCValue Target, uint64_t &FixedValue) override { if (Writer->is64Bit()) RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target, FixedValue); diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index fab0004343d..3cb8974f773 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -2681,8 +2681,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << " const SmallVectorImpl " << "&Operands);\n"; OS << " void convertToMapAndConstraints(unsigned Kind,\n "; - OS << " const SmallVectorImpl &Operands);\n"; - OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n"; + OS << " const SmallVectorImpl &Operands) override;\n"; + OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) override;\n"; OS << " unsigned MatchInstructionImpl(\n"; OS.indent(27); OS << "const SmallVectorImpl &Operands,\n" -- 2.34.1