From 1300b436731a1ffaf7545efe2ae51accc290d4c6 Mon Sep 17 00:00:00 2001 From: Zheng Yang Date: Fri, 24 Feb 2017 14:56:40 +0800 Subject: [PATCH] drm/rockchip: dw_hdmi: use crtc_clock as vpll clock rate adjusted_mode.crtc_clock is the real pixel clock rate. Change-Id: Iac242b89e3144bc53c40170c2cec0c0913ef6ee0 Signed-off-by: Zheng Yang --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 0a9121c461df..a771b0d2471e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -285,7 +285,9 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) if (WARN_ON(!crtc || !crtc->state)) return; - clk_set_rate(hdmi->vpll_clk, crtc->state->adjusted_mode.clock * 1000); + + clk_set_rate(hdmi->vpll_clk, + crtc->state->adjusted_mode.crtc_clock * 1000); switch (hdmi->dev_type) { case RK3288_HDMI: -- 2.34.1