From 13664a6194beb70d3efbf318adae5ebe51ddaef8 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 14 Oct 2005 04:55:10 +0000 Subject: [PATCH] add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/TargetSelectionDAG.td | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index ed63fcbd50d..702659a452f 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -45,6 +45,10 @@ class SDTCisVTSmallerThanOp : SDTypeConstraint { int OtherOperandNum = OtherOp; } +class SDTCisOpSmallerThanOp : SDTypeConstraint{ + int BigOperandNum = BigOp; +} + //===----------------------------------------------------------------------===// // Selection DAG Type Profile definitions. // @@ -77,6 +81,12 @@ def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc SDTCisSameAs<0, 1>, SDTCisFP<0> ]>; +def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround + SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> +]>; +def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend + SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> +]>; def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, SDTCisVTSmallerThanOp<2, 1> @@ -136,6 +146,9 @@ def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; +def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; +def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; + def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; -- 2.34.1