From 13b2781a0af169164d2017bf80d18123d513021e Mon Sep 17 00:00:00 2001
From: William Wu <william.wu@rock-chips.com>
Date: Wed, 17 May 2017 16:56:50 +0800
Subject: [PATCH] arm: dts: rockchip: add u2phy1 otg-port node for rk322x SoC

Change-Id: I42efd4227428df38c643c174fb2babcd61064a72
Signed-off-by: William Wu <william.wu@rock-chips.com>
---
 arch/arm/boot/dts/rk322x.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index e102ec692575..3946c8c0697a 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -271,6 +271,13 @@
 			clock-output-names = "usb480m_phy1";
 			status = "disabled";
 
+			u2phy1_otg: otg-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+
 			u2phy1_host: host-port {
 				#phy-cells = <0>;
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -701,6 +708,8 @@
 		reg = <0x30100000 0x20000>;
 		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
 		clock-names = "usbhost", "utmi";
 		status = "disabled";
 	};
@@ -711,6 +720,8 @@
 		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 		clock-names = "usbhost", "utmi";
+		phys = <&u2phy1_otg>;
+		phy-names = "usb";
 		status = "disabled";
 	};
 
-- 
2.34.1